AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 11

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Figure 1-7 • I/O Cluster Arrangement
Routing
The AX hierarchical routing structure ties the logic
modules, the embedded memory blocks, and the I/O
modules together
level, in and between SuperClusters, there are three local
routing structures: FastConnect, DirectConnect, and
CarryConnect routing. DirectConnects provide the highest
performance
connecting a C-cell to the adjacent R-cell. DirectConnects
do not require an antifuse to make the connection and
achieve a signal propagation time of less than 0.1 ns.
FastConnects
routing inside the SuperCluster and vertical routing to
the SuperCluster immediately below it. Only one
programmable connection is used in a FastConnect path,
delivering a maximum routing delay of 0.4 ns.
CarryConnects are used for routing carry logic between
adjacent SuperClusters. They connect the FCO output of
one two-bit, C-cell carry logic to the FCI input of the two-
bit, C-cell carry logic of the SuperCluster below it.
CarryConnects do not require an antifuse to make the
connection and achieve a signal propagation time of less
than 0.1 ns.
routing
provide
(Figure 1-8 on page
O
B
A
N
K
I
inside
high-performance,
RAM/
RAM/
RAM/
RAM/
FIFO
FIFO
FIFO
FIFO
4k
4k
4k
4k
the
1-6). At the lowest
SuperClusters
CoreTile
horizontal
Module
I/O
by
RX
v2.7
TX
RX
The next level contains the core tile routing. Over the
SuperClusters within a core tile, both vertical and
horizontal
respectively. At the chip level, vertical and horizontal
tracks extend across the full length of the device, both
north-to-south and east-to-west. These tracks are
composed of highway routing that extend the entire
length of the device (segmented at core tile boundaries)
as well as segmented routing of varying lengths.
Global Resources
Each family member has three types of global signals
available to the designer: HCLK, CLK, and GCLR/GPSET.
There are four hardwired clocks (HCLK) per device that
can directly drive the clock input of each R-cell. Each of
the four routed clocks (CLK) can drive the clock, clear,
preset, or enable pin of an R-cell or any input of a C-cell
(Figure 1-3 on page
Global clear (GCLR) and global preset (GPSET) drive the
clear and preset inputs of each R-cell as well as each I/O
Register on a chip-wide basis at power-up.
Each HCLK and CLK has an associated analog PLL (a total
of eight per chip). Each embedded PLL can be used for
clock delay minimization, clock delay adjustment, or
clock frequency synthesis. The PLL is capable of
InReg
I/O Module
B
TX
RX
OutReg
RX
tracks
Module
I/O
EnReg
1-3).
run
across
I/O Cluster
Axcelerator Family FPGAs
rows
or
columns,
1-5