AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 98

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Table 2-96 • FIFO Signal Description
2 -8 4
Signal
WCLK
FWEN
WD[N-1:0]
FULL
AFULL
AFVAL
RCLK
FREN
RD[N-1:0]
EMPTY
AEMPTY
AEVAL
PIPE
CLR
DEPTH
WIDTH
Axcelerator Family FPGAs
Direction
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Write clock (active either edge).
FIFO write enable. When this signal is asserted, the WD bus data is latched into the
FIFO, and the internal write counters are incremented.
Write data bus. The value N is dependent on the RAM configuration and can be 1,
2, 4, 9, 18, or 36.
Active high signal indicating that the FIFO is FULL. When this signal is set,
additional write requests are ignored.
Active high signal indicating that the FIFO is AFULL.
8-bit input defining the AFULL value of the FIFO.
Read clock (active either edge).
FIFO read enable.
Read data bus. The value N is dependent on the RAM configuration and can be 1,
2, 4, 9, 18, or 36.
Empty flag indicating that the FIFO is EMPTY. When this signal is asserted,
attempts to read the FIFO will be ignored.
Active high signal indicating that the FIFO is AEMPTY.
8-bit input defining the almost-empty value of the FIFO.
Sets the pipe option on or off.
Active high clear input.
Determines the depth of the FIFO and the number of FIFOs to be cascaded.
Determines the width of the dataword / width of the FIFO, and the number of the
FIFOs to be cascaded.
v2.7
Description