AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 74

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AX500-1BG896

Manufacturer Part Number
AX500-1BG896
Description
Axcelerator Family FPGAs
Manufacturer
ACTEL [Actel Corporation]
Datasheet
The ClockTileDist Cluster contains an HCLKMux (HM)
module for each of the four HCLK trees and a CLKMux
(CM) module for each of the CLK trees. The HCLK
branches then propagate horizontally through the
middle of the core tile to HCLKColDist (HD) modules in
every SuperCluster column. The CLK branches propagate
Figure 2-40 • CTD, CD, and HD Module Layout
Figure 2-41 • HCLK and CLK Distribution within a Core Tile
2 -6 0
Axcelerator Family FPGAs
v2.7
vertically through the center of the core tile to
CLKRowDist (RD) modules in every SuperCluster row.
Together, the HCLK and CLK branches provide for a low-
skew global fanout within the core tile
Figure
2-41).
(Figure 2-40
and

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