AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 79

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Table 2-79 • PLL Interface Signals (Continued)
Note: Not all signals are available to the user.
Figure 2-49 • PLL Logical Interface
PLL Configurations
The following rules apply to the different PLL inputs and
outputs:
Reference Clock
The RefCLK can be driven by
1. Global routed clocks (CLKE/F/G/H) or user-created
2. CLK1 output of an adjacent PLL
3. [H]CLKxP (single-ended or voltage-referenced)
4. [H]CLKxP/[H]CLKxN pair (differential modes like
Feedback Clock
The feedback clock can be driven by
2-66):
1. Global routed clocks (CLKE/F/G/H) or user-created
2. External [H]CLKxP/N I/O pad(s) from the adjacent PLL
3. An internal signal from the PLL block
Signal Name
PLLSEL
ROOTSEL
Lock
CLK1
CLK2
Note: If the input RefClk is taken outside its operating range, the outputs Lock, CLK1 and CLK2 are indeterminate.
clock network
LVPECL or LVDS)
clock network
cell
Core net
CLK net
I/O
Output
Output
Output
Type
Input
Input
[H]CLKINT
CLK1 (PLLn-1)
[H]CLKxP
[H]CLKxN
User Accessible
(Figure
FBINT
Yes
Yes
Yes
No
No
FBMuxSEL
(Figure 2-51 on page
2-50):
REFSEL
Allowable Values
RefCLK
FB
PLL
v2.7
CLK1
CLK2
Figure 2-50 • Reference Clock Connections
ROOTSEL & PLLSEL are used to select the source of the global
clock network
High value indicates PLL has locked
PLL clock output
PLL clock output
CLK1 (PLLn-1)
Non-clock
Pins
P
N
Any macro from the core, except HCLK nets
To PLLn+1
CLKINT
PLL
Regular, LVPECL, or LVDS IOPAD
Logic
INBUF
OUTSEL
CLK1
0
1
0
1
2
3
PLLSEL
Function
RefCLK
RefCLK
RefCLK
CLK Out
(Routed net out pin)
ROOTSEL
Axcelerator Family FPGAs
For cascading
PLL
PLL
PLL
[H]CLK
2-65