AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 28

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Figure 2-5 • I/O Cluster Interface
I/O Clusters
Each I/O cluster incorporates two I/O modules, four RX
modules and two TX modules, and a buffer module. In
turn, each I/O module contains one Input Register
(InReg), one Output Register (OutReg), and one Enable
Register (EnReg)
Using an I/O Register
To access the I/O registers, registers must be instantiated
in the netlist and then connected to the I/Os. Usage of
each I/O register (register combining) is individually
controlled and can be selected/deselected using the
PinEditor tool in Actel's Designer software. I/O register
combining can also be controlled at the device level,
affecting all I/Os. Please note, the I/O register option is
deselected by default in any given design.
In addition, Designer software provides a global option to
enable/disable the usage of registers in the I/Os. This option
is design-specific. The setting for each individual I/O
overrides this global option. Furthermore, the global set
2 -1 4
Axcelerator Family FPGAs
4. Please note that register combining for multi fanout nets is not supported.
routed input track
routed input track
routed input track
routed input track
output track
output track
(Figure
2-5).
DIN YOUT
DIN YOUT
DIN YOUT
DIN YOUT
Y
Y
OutREg
OutREg
EnReg
EnReg
InReg
InReg
DCIN
DCIN
4
routed input track
routed input track
routed input track
routed input track
I/O CLUSTER
output track
output track
v2.7
fuse option in the Designer software, when checked, causes
all I/O registers to output logic High at device power-up.
Using the Weak Pull-Up and Pull-Down
Circuits
Each Axcelerator I/O comes with a weak pull-up/down
circuit (on the order of 10 kΩ). I/O macros are provided
for combinations of pull up/down for LVTTL, LVCMOS
(2.5V, 1.8V, and 1.5V) standards. These macros can be
instantiated if a keeper circuit for any input buffer is
required.
Customizing the I/O
• A five-bit programmable input delay element is
associated with each I/O. The value of this delay is
set on a bank-wide basis
It is optional for each input buffer within the bank
(i.e. the user can enable or disable the delay
element for the I/O). When the input buffer drives a
register within the I/O, the delay element is
UON
UOP
OEN
OEP
UIP
UIN
drive strength
drive strength
slew rate
slew rate
programmable delay
programmable delay
P PAD
N PAD
(Table 2-14 on page
V
V
REF
REF
I/O
I/O
2-15).