AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 32

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

User I/O Naming Conventions
Due to the complex and flexible nature of the Axcelerator family’s user I/Os, a naming scheme is used to show the
details of the I/O. The naming scheme explains to which bank an I/O belongs, as well as the pairing and pin polarity for
differential I/Os
Figure 2-7 • I/O Bank and Dedicated Pin Layout
Figure 2-8 • General Naming Schemes
2 -1 8
Axcelerator Family FPGAs
GND
V
V
GND
V
GND
V
GND
V
GND
V
GND
GND
V
CCDA
CCA
CCA
CCI
CCDA
CCI
CCDA
P - Positive Pin/ N- Negative Pin
7
6
(Figure
clockwise from IOB NW
clockwise from IOB NW
unimplemented feature
Bank I/D 0 through 7,
Corner1
Corner4
bank, starting at 00,
and can be ignored.
Pair number in the
2-7).
Fx refers to an
I/O BANK 0
I/O BANK 5
IOxxXBxFx
AX125
Examples:
IO12PB1F1 is the positive pin of the thirteenth pair of the
IOxxXBxFx/special_function_name
IOxxPB1Fx/xCLKx this pin can be configured as a clock
v2.7
first I/O bank (IOB NE). IO12PB1 combined
with IO12NB1 form a differential pair.
For those I/Os that can be employed
either as a user I/O or as a special
function, the following nomenclature
is used:
I/O BANK 1
I/O BANK 4
input or as a user I/O.
Corner2
Corner3
GND
V
V
GND
V
GND
GND
V
V
GND
V
GND
GND
V
CCDA
CCDA
CCI
CCA
CCI
CCA
CCDA
3
2