AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 86

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Embedded Memory
The AX architecture provides extensive, high-speed
memory resources to the user. Each 4,608 bit block of
RAM contains its own embedded FIFO controller,
allowing the user to configure each block as either RAM
or FIFO.
To meet the needs of high performance designs, the
memory blocks operate in synchronous mode for both
read and write operations. However, the read and write
clocks are completely independent, and each may
operate up to and above 500 MHz.
No additional core logic resources are required to
cascade the address and data buses when cascading
different RAM blocks. Dedicated routing runs along each
column of RAM to facilitate cascading.
The AX memory block includes dedicated FIFO control
logic to generate internal addresses and external flag
logic (FULL, EMPTY, AFULL, AEMPTY). Since read and
write operations can occur asynchronously to one
another, special control circuitry is included to prevent
metastability, overflow, and underflow. A block diagram
of the memory module is illustrated in
During RAM operation, read (RA) and write (WA)
addresses are sourced by user logic and the FIFO
controller is ignored. In FIFO mode, the internal
addresses are generated by the FIFO controller and
routed to the RAM array by internal MUXes. Enables
with programmable polarity are provided to create
upper address bits for cascading up to 16 memory blocks.
When cascading memory blocks, the bussed signals WA,
WD, WEN, RA, RD, and REN are internally linked to
eliminate external routing congestion.
Table 2-85 • Memory Block WxD Options
2 -7 2
Axcelerator Family FPGAs
Data-word (in bits)
18
36
1
2
4
9
Depth
4,096
2,048
1,024
Figure
512
256
128
2-57.
v2.7
Figure 2-57 • Axcelerator Memory Module
RAM
Each memory block consists of 4,608 bits that can be
organized as 128x36, 256x18, 512x9, 1kx4, 2kx2, or 4kx1
and are cascadable to create larger memory sizes. This
allows built-in bus width conversion
block has independent read and write ports which
enable simultaneous read and write operations.
Address Bus
RA/WA[11:0]
RA/WA[10:0]
RA/WA[9:0]
RA/WA[8:0]
RA/WA[7:0]
RA/WA[6:0]
RA [K:0]
REN
RCLK
WD [(M-1):0]
WA [J:0]
WEN
PIPE
RW [2:0]
WW [2:0]
WCLK
RD [(N-1):0]
RD/WD[17:0]
RD/WD[35:0]
RD/WD[1:0]
RD/WD[3:0]
RD/WD[8:0]
Data Bus
RD/WD[0]
(Table
2-85). Each