AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 12

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Figure 1-8 • AX Routing Structures
operating with input frequencies ranging from 14 MHz
to 200 MHz and can generate output frequencies
between 20 MHz and 1 GHz. The clock can be either
divided or multiplied by factors ranging from 1 to 64.
Additionally, multiply and divide settings can be used in
any combination as long as the resulting clock frequency
is between 20 MHz and 1 GHz. Adjacent PLLs can be
cascaded to create complex frequency combinations.
The PLL can be used to introduce either a positive or a
negative clock delay of up to 3.75 ns in 250 ps
increments. The reference clock required to drive the PLL
can be derived from three sources: external input pad
(either single-ended or differential), internal logic, or the
output of an adjacent PLL.
Low Power (LP) Mode
The AX architecture was created for high-performance
designs but also includes a low power mode (activated via
the LP pin). When the low power mode is activated, I/O
banks can be disabled (inputs disabled, outputs tristated),
and PLLs can be placed in a power-down mode. All
internal register states are maintained in this mode.
Furthermore, individual I/O banks can be configured to
opt out of the LP mode, thereby giving the designer access
to critical signals while the rest of the chip is in low power
mode.
The power can be further reduced by providing an
external voltage source (V
the internal charge pump (See
page 2-89
1 -6
Axcelerator Family FPGAs
for more information).
PUMP
) to the device to bypass
"Low Power Mode" on
v2.7
Design Environment
The Axcelerator family of FPGAs is fully supported by both
Actel's Libero™ Integrated Design Environment and
Designer FPGA Development software. Actel Libero IDE is
an integrated design manager that seamlessly integrates
design tools while guiding the user through the design
flow, managing all design and log files, and passing
necessary design data among tools. Additionally, Libero
IDE allows users to integrate both schematic and HDL
synthesis into a single flow and verify the entire design in
a single environment (see the
located on Actel’s website). Libero IDE includes Synplify
Actel Edition (AE) from Synplicity
Mentor Graphics
Mentor
SynaptiCAD
Actel's Designer software is a place-and-route tool and
provides a comprehensive suite of backend support tools
for FPGA development. The Designer software includes
the following:
• Timer – a world-class integrated static timing analyzer
• NetlistViewer – a design netlist schematic viewer
• ChipPlanner – a graphical floorplanner viewer and editor
• SmartPower – allows the designer to quickly estimate
• PinEditor – a graphical application for editing pin
• I/O Attribute Editor – displays all assigned and
and constraints editor which support timing-driven
place-and-route
the power consumption of a design
assignments and I/O attributes
unassigned I/O macros and their attributes in a
spreadsheet format
Graphics,
®
, and Designer software from Actel.
®
, ModelSim
WaveFormer
®
Libero IDE Flow
®
HDL Simulator from
, ViewDraw
Lite™
®
AE
AE from
diagram
from
®