AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 87

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Clocks
The RCLK and the WCLK have independent source
polarity selection and can be sourced by any global or
local signal.
RAM Configurations
The AX architecture allows the read side and write side
of RAMs to be organized independently, allowing for
bus conversion. For example, the write side can be set to
256x18 and the read side to 512x9.
Both the write width and read width for the RAM blocks
can be specified independently and changed dynamically
with the WW (write width) and RW (read width) pins.
Table 2-86 • RAM Signal Description
Table 2-87 • Allowable RW and WW Values
Signal
WCLK
WA[J:0]
WD[M-1:0]
RCLK
RA[K:0]
RD[N-1:0]
REN
WEN
RW[2:0]
WW[2:0]
Pipe
RW(2:0)
000
001
010
011
100
101
11x
Direction
Input
Input
Input
Input
Input
Output
Input
Input
Input
Input
Input
Write clock (can be active on either edge).
Write address bus.The value J is dependent on the RAM configuration and the number of cascaded
memory blocks. The valid range for J is from 6 to15.
Write data bus. The value M is dependent on the RAM configuration and can be 1, 2, 4, 9, 18, or
36.
Read clock (can be active on either edge).
Read address bus. The value K is dependent on the RAM configuration and the number of cascaded
memory blocks. The valid range for K is from 6 to 15.
Read data bus. The value N is dependent on the RAM configuration and can be 1, 2, 4, 9, 18, or 36.
Read enable. When this signal is valid on the active edge of the clock, data at location RA will be
driven onto RD.
Write enable. When this signal is valid on the active edge of the clock, WD data will be written at
location WA.
Width of the read operation dataword.
Width of the write operation dataword.
Sets the pipe option to be on or off.
WW(2:0)
v2.7
000
001
010
011
100
101
11x
The D x W different configurations are: 128 x 36,
256 x 18, 512 x 9, 1k x 4, 2k x 2, and 4k x 1. The allowable
RW and WW values are shown in
When widths of one, two, and four are selected, the
ninth bit is unused. For example, when writing nine-bit
values and reading four-bit values, only the first four bits
and the second four bits of each nine-bit value are
addressable for read operations. The ninth bit is not
accessible. Conversely, when writing four-bit values and
reading nine-bit values, the ninth bit of a read operation
will be undefined.
Note that the RAM blocks employ little-endian byte
order for read and write operations.
Description
Axcelerator Family FPGAs
256 x 18
128 x 36
Table
reserved
512 x 9
D x W
4k x 1
2k x 2
1k x 4
2-87.
2-73