AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 85

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Clock Skew Minimization
Figure 2-56
clock network and the input clock. The input clock is fed to the reference clock input of the PLL. The output clock (CLK2)
feeds a routed clock network. The feedback input to the PLL uses a clock input delayed by a routing network. The PLL then
adjusts the phase of the input clock to match the delayed clock, thus providing nearly zero effective skew between the two
clocks. Refer to Actel’s
Figure 2-56 • Using the PLL for Clock Deskewing
Input Clock
indicates how feedback from the clock network can be used to create minimal skew between the distributed
Axcelerator Family PLL and Clock Management
PowerDown
133 MHz
FBMuxSel
FB
RefCLK
Delay Line
Delay Line
DelayLine
5
Q
Q
CLR
SET
D
DividerI
/i Delay
Match
6
÷1
/i
v2.7
LowFreq
application note for more information.
Clock Network
PLL
Osc
3
133 MHz
Axcelerator Family FPGAs
DividerJ
/i Delay
Match
6
/j
133 MHz
Lock
CLK1
CLK2
2-71