AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 63

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Buffer Module
Introduction
An additional resource inside each SuperCluster is the Buffer (B) module
constraint is applied to a design, the synthesis tool inserts buffers as needed. The buffer module has been added to
the AX architecture to avoid logic duplication resulting from the hard fanout constraints. The router utilizes this logic
resource to save area and reduce loading and delays on medium-to-high-fanout nets.
Timing Models and Waveforms
Figure 2-33 • Buffer Module Timing Model
Figure 2-34 • Buffer Module Waveform
Timing Characteristics
Table 2-63 • Buffer Module
Parameter
Buffer Module Propagation Delays
t
BFPD
Worst-Case Commercial Conditions V
Any input to output Y
Description
IN
OUT
GND
50%
IN
t
BFPD
CCA
V
CCA
= 1.425V, V
50%
50%
V
CCA
Min.
v2.7
'–2' Speed
CCI
t
BFPD
= 3.0V, T
Max.
0.12
50%
OUT
GND
J
= 70°C
Min.
(Figure 1-4 on page
'–1' Speed
Max.
0.14
Axcelerator Family FPGAs
Min.
'Std' Speed
1-3). When a fanout
Max.
0.16
Units
ns
2-49