AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 25

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

The differential amplifier supply voltage V
connected to 3.3V.
A user can gain access to the various I/O standards in
three ways:
Table 2-8 • I/O Standards Supported by the Axcelerator Family
Table 2-9 • Supply Voltages
Table 2-10 • I/O Features Comparison
I/O Standard
LVTTL
LVCMOS 2.5V
LVCMOS 1.8V
LVCMOS 1.5V (JDEC8-11)
3.3V PCI/PCI-X
GTL+ 3.3V
GTL+ 2.5V
HSTL Class 1
SSTL3 Class 1 and II
SSTL2 Class1 and II
LVDS
LVPECL
Note: *2.5V GTL+ is not supported across the full military temperature range.
I/O Assignment
LVTTL
3.3V PCI, 3.3V PCI-X
LVCMOS2.5V
LVCMOS1.8V
LVCMOS1.5V (JESD8-11)
Voltage-Referenced Input Buffer
Differential, LVDS/LVPECL, Input
Differential, LVDS/LVPECL, Output
Notes:
1. Can be implemented with an IDT bus switch.
2. Can be implemented with an external resistor.
3. The OE input of the output buffer must be deasserted permanently (handled by software).
4. The OE input of the output buffer must be asserted permanently (handled by software).
• Instantiate specific library macros that represent
the desired specific standard
V
1.5V
1.5V
1.5V
1.5V
CCA
*
Input/Output Supply
V
1.5V
1.8V
2.5V
3.3V
CCI
Voltage (V
Clamp Diode
3.3
2.5
1.8
1.5
3.3
3.3
2.5
1.5
3.3
2.5
2.5
3.3
Yes
No
No
No
No
No
No
No
CCDA
CCI
)
should be
Hot Insertion
Input Tolerance
v2.7
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Input Reference Voltage
3.3V
3.3V
3.3V
3.3V
Please refer to the
Devices
Guide
• Use generic I/O macros and then use Actel
• A combination of the first two methods.
Designer’s PinEditor to specify the desired I/O
standards (please note that this is not applicable
to differential standards)
for more details.
(V
application note and the
0.75
1.25
5V Tolerance
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1.0
1.0
1.5
REF
Yes
)
Yes
No
No
No
No
No
No
1, 2
1
I/O Features in Axcelerator Family
Input Buffer
Board Termination Voltage
Output Drive Level
Disabled
Enabled
Axcelerator Family FPGAs
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Antifuse Macro Library
1.5V
1.8V
2.5V
3.3V
(V
0.75
1.25
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1.2
1.2
1.5
Output Buffer
TT
)
Disabled
Enabled
4
3
2-11