AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 76

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Implementation Example:
Figure 2-47
non-clock signal pins (INBUF to PLLINT). The CLK1 output of PLLE is being fed to the RefCLK input of PLLF. The CLK2
output of PLLE is driving logic (via PLLOUT). In turn, this logic is driving the global resource CLKE. PLLF is driving both
CLKF and CLKG global resources.
Figure 2-45 • Example of HCLKA driven from a PLL with External Clock Source
Figure 2-46 • Example of PLLINT and PLLOUT Usage
Figure 2-47 • Complex Clock Distribution Example
2 -6 2
Axcelerator Family FPGAs
HCLKAP
HCLKAN
shows a complex clock distribution example. The reference clock (RefCLK) of PLLE is being sourced from
N
P
Non-Clock
Pins
Logic
PLLINT
INBUF
RefCLK
RefCLK
FB
FB
PLLF
PLLE
CLK2
CLK2
PLLINT
CLK1
CLK1
PLLRCLK
RefCLK
FB
FB
RefCLK
PLLOUT
PLLRCLK
PLLRCLK
PLLA
v2.7
PLLA
CLK2
CLK1
CLKF
CLKG
CLK1
CLK2
Logic
PLLHCLK
PLLOUT
CLKINT
PLLHCLK
HCLKA
Network
Logic
CLKE
Network
HCLKA