AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 73

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Global Resource Distribution
At the root of each global resource is a PLL. There are
two groups of four PLLs for every device. One group,
located at the center of the north edge (in the I/O ring)
of the chip, sources the four HCLKs. The second group,
located at the center of the south edge (again in the I/O
ring), sources the four CLKs
Figure 2-38 • PLL Group
Figure 2-39 • Example of HCLK and CLK Distributions on the AX2000
ClockTileDist Cluster
(Figure
2-38).
PLL Group
HCLK
HCLKA
CLKE
P N
P N
PLL
PLL
4
HCLKB HCLKC HCLKD
P N
CLKF
P N
PLL
PLL
PLL Cluster
PLL Cluster
v2.7
CLKG
P N
P N
PLL
PLL
Regardless of the type of global resource, HCLK or CLK,
each of the eight resources reach the ClockTileDist (CTD)
Cluster located at the center of every core tile with zero
skew. From the ClockTileDist Cluster, all four HCLKs and
four CLKs are distributed through the core tile
39).
CLKH
P N
P N
PLL
PLL
PLL Group
CLK
Axcelerator Family FPGAs
4
(Figure 2-
2-59