AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 55

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit
is carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination. The
voltage swing between these two signal lines is approximately 850 mV.
Figure 2-26 • LVPECL Board-Level Implementation
The LVPECL circuit is similar to the LVDS scheme. It requires four external resistors, three for the driver and one for the
receiver. The values for the three driver resistors are different from that of LVDS since the output voltage levels are
different. Please note that the V
Table 2-58 • DC Input and Output Levels
Table 2-59 • AC Waveforms, Measuring Points, and Capacitive Loads
DC Parameter
V
V
V
V
V
Differential Input Voltage
* Measuring Point = V
CCI
OH
OL
IH
IL
OUTBUF_LVPECL
Input Low (V)
1.6-0.3
trip
FPGA
OH
Min.
0.96
1.49
0.86
1.8
0.3
levels are 200 mV below the standard LVPECL levels.
N
P
Min.
3
100Ω
100Ω
Max.
2.125
2.11
1.27
2.72
Input High (V)
1.6+0.3
187Ω
v2.7
Min.
1.92
1.06
1.49
0.86
0.3
ZO=50Ω
ZO=50Ω
Typ.
3.3
Max.
2.125
2.28
1.43
2.72
100Ω
N
P
Min.
2.13
1.49
0.86
1.3
0.3
Measuring Point* (V)
FPGA
–
+
Max.
3.6
Axcelerator Family FPGAs
Max.
2.125
INBUF_LVPECL
1.6
2.41
1.57
2.72
Units
V
V
V
V
V
V
2-41