AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 95

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

FIFO Flag Logic
The FIFO is user configurable into various DEPTHs and
WIDTHs.
details.
For example, if four blocks are cascaded as a 1kx16 FIFO
with each block having a 1kx4 aspect ratio, bits 11 to 2 of
the address will be used to specify locations within each
Note: Inactive counter bits are set to zero.
Figure 2-62 • FIFO Address Counters
Table 2-93 • FIFO Flag Logic
Mode
Non-cascade
Cascade 2 blocks
Cascade 4 blocks
Cascade 8 blocks
Cascade 16 blocks
• Bits 11 to 5 are active for all modes.
• As the data word size is reduced, more least-
• As the number of cascaded blocks increases, the
significant bits are added to the address.
number of significant bits in the address increases.
Figure 2-62
Mode when
Cas 16 blks
Cas 8 blks
Cas 2 blks
by 4
by 2
by 1
Active
Cas 4 blks
by 36
by 18
by 9
Inactive AEVAL/AFVAL bits
shows the FIFO address counter
always active
CNTR [11:5]
CNTR [14]
CNTR [13]
CNTR [15]
CNTR [12]
Counter
CNTR [4]
CNTR [3]
CNTR [2]
CNTR [1]
CNTR [0]
activate
activate
activate
activate
activate
activate
activate
activate
activate
Bits
None
[7:4]
[7:5]
[7:6]
[7]
R/W ADD[7:5]
R/W EN[3]
R/W EN[2]
R/W EN[1]
R/W EN[0]
R/W ADD[11:8]
R/W ADD[4]
R/W ADD[3]
R/W ADD[2]
R/W ADD[1]
R/W ADD[0]
FIFO Address
FIFO Address Counters
Inactive DIFF bits (set to 0)
Alignment of
Threshold bits
CNTR [15:0]
AEVAL/AFVAL[5]
AEVAL/AFVAL[4]
not compared
not compared
not compared
not compared
AEVAL/AFVAL[6]
AEVAL/AFVAL[3:0]
not compared
not compared
AEVAL/AFVAL[7]
v2.7
RAM block, whereas bits 13 and 12 will be used to specify
the RAM block.
The AFULL and AEMPTY flag threshold values are
programmable. The threshold values are AFVAL and
AEVAL, respectively. Although the trigger threshold for
each flag is defined with eight bits, the effective number
of threshold bits in the comparison depends on the
configuration. The effective number of threshold bits
corresponds to the range of active bits in the FIFO
address space
[15:12]
[15:13]
[15:14]
None
[15]
128x36
[12:W] [13:W]
[11:5]
256x18
Variable Active Address Space
(Table
>> WEN [4:0], WAD [11:0]
>> REN [4:0], RAD [11:0]
[11:4]
512x9
2-93).
DIFF comparison to AFVAL/AEVAL
[14:W]
[11:3]
1kx4
DIFF[11:8] withAE/FVAL[3:0]
DIFF[12:8] withAE/FVAL[4:0]
DIFF[13:8] withAE/FVAL[5:0]
DIFF[14:8] withAE/FVAL[6:0]
DIFF[15:8] withAE/FVAL[7:0]
[11:2]
2kx2
Axcelerator Family FPGAs
[15:W]
[11:1]
4kx1
[11:0]
2-81