AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 24

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

JTAG/Probe Pins
PRA/B/C/D
The Probe pins are used to output data from any user-
defined design node within the device (controlled with
Silicon Explorer II). These independent diagnostic pins
can be used to allow real-time diagnostic output of any
signal path within the device. The pins’ probe
capabilities can be permanently disabled to protect
programmed design confidentiality. The probe pins are
of LVTTL output levels.
TCK
Test clock input for JTAG boundary-scan testing and
diagnostic probe (Silicon Explorer II).
TDI
Serial input for JTAG boundary-scan testing and
diagnostic probe. TDI is equipped with an internal 10 kΩ
pull-up resistor.
TDO
Serial output for JTAG boundary-scan testing.
TMS
The TMS pin controls the use of the IEEE 1149.1
boundary-scan pins (TCK, TDI, TDO, TRST). TMS is
equipped with an internal 10 k
TRST
The TRST pin functions as an active-low input to
asynchronously initialize or reset the boundary scan circuit.
The TRST pin is equipped with a 10 k
Special Functions
LP
The LP pin controls the low power mode of Axcelerator
devices. The device is placed in the low power mode by
connecting the LP pin to logic high. To exit the low
power mode, the LP pin must be set Low. Additionally,
the LP pin must be set Low during chip powering-up or
chip powering-down operations. See
Mode" on page 2-89
NC
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
2 -1 0
Axcelerator Family FPGAs
2. Do not use an external resister to pull the I/O above V
voltage level will be degraded due to a small I/O current, which exists when the I/O is pulled up above V
Probe A/B/C/D
Test Clock
Test Data Input
Test Data Output
Test Mode Select
Boundary Scan Reset Pin
Low Power Pin
No Connection
for more details.
Ω
pull-up resistor.
Ω
pull-up resistor.
"Low Power
CCI
v2.7
for a higher logic “1” voltage level. The desired higher logic “1”
User I/Os
Introduction
The Axcelerator family features a flexible I/O structure,
supporting a range of mixed voltages (1.5V, 1.8V, 2.5V,
and 3.3V) with its bank-selectable I/Os.
page 2-11
Axcelerator
compares the features of the different I/O standards.
Each I/O provides programmable slew rates, drive
strengths, and weak pull-up and weak pull-down circuits.
I/O standards, except 3.3V PCI and 3.3V PCI-X, are
capable of hot insertion. 3.3V PCI and 3.3V PCI-X are 5V
tolerant with the aid of an external resistor.
The input buffer has an optional user-configurable delay
element. The element can reduce or eliminate the hold
time requirement for input signals registered within the
I/O cell. The value for the delay is set on a bank-wide
basis. Note that the delay WILL be a function of process
variations as well as temperature and voltage changes.
Each I/O includes three registers: an input (InReg), an
output (OutReg), and an enable register (EnReg). I/Os are
organized into banks, and there are eight banks per
device — two per side
bank has a common V
For voltage-referenced I/Os, each bank also has a
common reference-voltage bus, V
have a common voltage for an entire I/O bank, its
location is user-selectable. In other words, any user I/O in
the bank can be selected to be a V
The location of the V
to the following rules:
• Any pin that is assigned as a V
• I/O pad locations listed as no connects are counted
• Dedicated I/O pins (GND, V
• The two user I/O pads immediately adjacent on each
maximum of eight user I/O pad locations in each
direction (16 total maximum) within the same I/O
bank.
as part of the 16 maximum. In many cases, this
leads to fewer than eight user I/O package pins in
each direction being controlled by a V
part of the 16.
side of the V
as an input. The exception is when there is a V
GND pair separating the V
pad location.
contains the I/O standards supported by the
2
family,
REF
REF
CCI
pin (four in total) may only be used
(Figure 2-6 on page
and
pin should be selected according
, the supply voltage for its I/Os.
Table 2-10
REF
REF
CCI
CCI
REF
pin and the user I/O
.
.
...) are counted as
. While V
REF
on
2-15). Each I/O
can control a
Table 2-8 on
REF
page 2-11
REF
pin.
must
CCI
/