AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 71

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Routed Clocks
The routed clock (CLK) is a low-skew network that can
drive the clock inputs of all sequential modules in the
device (logically equivalent to the HCLK), but has the
added flexibility in that it can drive the S0 (Enable), S1,
PSET, and CLR input of a register (R-cells and I/O
Timing Characteristics
Table 2-74 • AX125 Routed Array Clock Networks
Table 2-75 • AX250 Routed Array Clock Networks
Parameter
Routed Array Clock Networks
t
t
t
t
t
t
t
Parameter
Routed Array Clock Networks
t
t
t
t
t
t
t
RCKL
RCKH
RPWH
RPWL
RCKSW
RP
RMAX
RCKL
RCKH
RPWH
RPWL
RCKSW
RP
RMAX
Worst-Case Commercial Conditions V
Worst-Case Commercial Conditions V
Input Low to High
Input High to Low
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
Minimum Period
Maximum Frequency
Input Low to High
Input High to Low
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
Minimum Period
Maximum Frequency
Description
Description
CCA
CCA
= 1.425V, V
= 1.425V, V
Min.
Min.
0.57
0.52
1.15
0.57
0.52
1.15
'–2' Speed
'–2' Speed
v2.7
Max.
registers) as well as any of the inputs of any C-cell in the
device. This allows CLKs to be used not only as clocks, but
also for other global signals or high fanout nets. All four
CLKs are available everywhere on the chip.
Max.
3.08
3.13
0.35
870
2.52
2.59
0.35
CCI
CCI
870
= 3.0V, T
= 3.0V, T
Min.
Min.
0.64
0.59
1.31
0.64
0.59
1.31
'–1' Speed
'–1' Speed
J
J
= 70°C
= 70°C
Max.
Max.
3.50
3.56
0.39
763
2.95
2.87
0.39
763
Min.
Min.
0.75
0.69
1.54
0.75
0.69
1.54
'Std' Speed
'Std' Speed
Axcelerator Family FPGAs
Max.
Max.
4.12
4.19
0.46
649
3.37
3.47
0.46
649
Units
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2-57