AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 22

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Timing Model
Note: Worst case timing data for the AX1000, –2 speed grade
Figure 2-1 • Worst Case Timing Data
Hardwired Clock – Using LVTTL 24mA High
Slew Clock I/O
2 -8
LVDS
External Setup
Clock-to-Out (Pad-to-Pad)
Axcelerator Family FPGAs
Hardwired or
Routed Clock
Hardwired Clock
t
F
F
LVPECL
HCKH
MAX
MAX
= (t
= (1.72 + 0.53 + 0.23) – 3.02 = –0.54 ns
= t
= 3.02 + 0.67 + 0.45 + 3.03 = 7.17 ns
(Non- registered)
(external) = 350 MHz
(internal) = 870 MHz
t
HCKL
= 3.03 ns
DP
DP
I/O Module
= 1.84 ns
+ t
+
+ t
RD2
RCO
+ t
+
t
t
HCKL
RCKL
t
+ t
DP
SUD)
t
t
(Registered)
SUD
ICKLQ
I/O Module
= 1.70 ns
RD1
= 3.02 ns
= 3.08 ns
= 0.23 ns
– t
= 0.67 ns
+ t
HCKL
PYs
t
RD2
t
BFPD
Module
= 0.53 ns
Buffer
Register Cell
t
t
= 0.12 ns
RCO
SUD
D
= 0.23 ns
= 0.67 ns
Q
t
Combinatorial
Combinatorial
t
PDC
RD1
t
PD
= 0.57 ns
= 0.45 ns
= 0.74 ns
Cell
Cell
FCO
Combinatorial
t
PD
Carry Chain
Y
v2.7
= 0.74 ns
Cell
Routed Clock – Using LVTTL 24mA High Slew
Clock I/O
External Setup
Clock-to-Out (Pad-to-Pad)
t
BFPD
Y
Combinatorial
Module
Buffer
t
CCY
= 0.12 ns
Cell
= 0.61 ns
t
t
t
t
t
RD1
RD2
RD3
RCO
SUD
Register Cell
= (t
= (1.72 + 0.53 + 0.23) – 3.13 = –0.65 ns
= t
= 3.13 + 0.67 + 0.45 + 3.03 = 7.28 ns
= 0.45 ns
= 0.53 ns
= 0.56 ns
= 0.67 ns
= 0.23 ns
RCKH
D
DP
+ t
Q
t
F
F
(Nonregistered)
Routed Clock
+ t
t
RCKL
MAX
MAX
RD2
PY
(Nonregistered)
I/O Module
t
RCO
I/O Module
PY
= 2.28 ns
t
Module
= 3.08 ns
(external) = 350 MHz
(internal) = 870 MHz
Buffer
BPFD
+ t
= 3.03 ns
+ t
SUD)
= 0.12 ns
I/O
I/O
RD1
– t
t
t
+ t
OCLKY
SUD
RCKH
I/O Module
PY
= 0.23 ns
D
= 0.67 ns
LVTTL
Output Drive
Strength = 4 (24mA)
High Slew Rate
LVPECL
Q
t
PY
= 1.01 ns
GTL + 3.3V