AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 83

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Sample Implementations
Frequency Synthesis
Figure 2-53
to multiply a 155.5 MHz external clock up to 622 MHz.
Note that the same PLL schematic could use an external
350 MHz clock, which is divided down to 155 MHz by the
FPGA internal logic.
Figure 2-53 • Using the PLL 155.5 MHz In, 622 MHz Out
Figure 2-54 • Using the PLL 155 MHz In, 133 MHz Out
RefCLK
155 MHz
FB
155.5 MHz
PowerDown
FB
PowerDown
RefCLK
FBMuxSel
illustrates an example where the PLL is used
FBMuxSel
Delay Line
Delay Line
DelayLine
Delay Line
Delay Line
DelayLine
5
5
/i Delay
DividerI
Match
/i Delay
Match
DividerI
6
÷6
6
/i
÷4
/i
155 MHz
155 MHz
v2.7
LowFreq
LowFreq
Figure 2-54
synthesize a 133 MHz output clock from a 155 MHz input
reference clock. The input frequency of 155 MHz is
multiplied by 6 and divided by 7, giving a CLK1 output
frequency of 132.86 MHz. When dividers are used, a
given ratio can be generated in multiple ways, allowing
the user to stay within the operating frequency ranges of
the PLL.
PLL
Yes
PLL
3
Osc
3
Osc
illustrates the PLL using both dividers to
930 MHz
/j Delay
DividerJ
/j Delay
Match
DividerJ
Match
Axcelerator Family FPGAs
6
6
/7
/j
/j
132.8 MHz
Lock
622 MHz
Lock
CLK1
CLK2
CLK2
CLK1
2-69