AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 75

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

The HM and CM modules can select between:
This allows each core tile to have eight clocks
independent of the other core tiles in the device.
Both HCLK and CLK are segmentable, meaning that
individual branches of the global resource can be used
independently.
Like the HM and CM modules, the HD and RD modules
can select between:
The AX architecture is capable of supporting a large
number of local clocks – 24 segments per HCLK driving
north-south and 28 segments per CLK driving east-west
per core tile.
Actel's
advantage of the segmented clock structure found in
Axcelerator devices by turning off any unused clock
segments. This results in not only better performance but
also lower power consumption.
Global Resource Access Macros
Global resources can be driven by one of three sources:
external pad(s), an internal net, or the output of a PLL.
These connections can be made by using one of three
types of macros: CLKBUF, CLKINT, and PLLCLK.
CLKBUF and HCLKBUF
Figure 2-42 • CLKBUF and HCLKBUF
• The HCLK or CLK source respectively
• A local signal routed on generic routing resources
• The HCLK or CLK source from the HM or CM
• A local signal routed on generic routing resources
CLKBUF (HCLKBUF) is used to drive a CLK (HCLK) from
external pads. These macros can be used either
generically or with the specific I/O standard desired
(e.g.
(Figure
Package pins CLKEP and CLKEN are associated with
CLKE; package pins HCLKAP and HCLKAN are
associated with HCLKA, etc.
Note that when CLKBUF (HCLKBUF) is used with a
single-ended I/O standard, it must be tied to the P-
pad of the CLK (HCLK) package pin. In this case, the
CLK (HCLK) N-pad can be used for user signals.
module respectively
P
N
Designer
CLKBUF_LVCMOS25,
2-42).
software’s
CLKBUF
HCLKBUF
place-and-route
HCLKBUF_LVDS,
Clock
Network
takes
etc.)
v2.7
CLKINT and HCLKINT
Figure 2-43 • CLKINT and HCLKINT
PLLRCLK and PLLHCLK
Figure 2-44 • PLLRCLK and PLLHCLK
Using Global Resources with PLLs
Each global resource has an associated PLL at its root. For
example, PLLA can drive HCLKA, PLLE can drive CLKE, etc.
(Figure 2-45 on page
In addition, each clock pin of the package can be used to
drive either its associated global resource or PLL. For
example, package pins CLKEP and CLKEN can drive either
the RefCLK input of PLLE or CLKE.
There are two macros required when interfacing the
embedded PLLs with the global resources: PLLINT and PLLOUT.
PLLINT
This macro is used to drive the RefCLK input of the PLL
internally from user signals.
PLLOUT
This macro is used to connect either the CLK1 or CLK2
output of a PLL to the regular routing network
46 on page
CLKINT (HCLKINT) is used to access the CLK (HCLK)
resource internally from the user signals
PLLRCLK (PLLHCLK) is used to drive global resource
CLK (HCLK) from a PLL
RefCLK
FB
Logic
2-62).
PLL
CLK1
CLK2
2-62).
(Figure
HCLKINT
CLKINT
Axcelerator Family FPGAs
PLLRCLK
PLLHCLK
2-44).
Clock
Network
(Figure
Clock
Network
(Figure 2-
2-43).
2-61