AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 97

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

The active-high CLR pin is used to reset the FIFO to the
empty state, which sets FULL and AFULL low, and EMPTY
and AEMPTY high.
Assuming that the EMPTY flag is not set, new data is
read from the FIFO when REN is valid on the active edge
of the clock. Write and read transfers are described with
timing requirements in
page
Glitch Elimination
An analog filter is added to each FIFO controller to
guarantee glitch-free FIFO-flag logic.
Figure 2-64 • Overflow and Underflow Control
FIFO Configurations
Unlike the RAM, the FIFO's write width and read width
cannot be specified independently. For the FIFO, the
write and read widths must be the same. The WIDTH pins
are used to specify one of six allowable word widths, as
shown in
The DEPTH pins allow RAM cells to be cascaded to create
larger FIFOs. The four pins allow depths of 2, 4, 8, and 16
to be specified.
FIFO depth options for various data width and memory
blocks.
Interface
Figure 2-65
Axcelerator FIFO module.
Cascading FIFO Blocks
FIFO blocks can be cascaded to create deeper FIFO
functions. When building larger FIFO blocks, if the word
width can be fractured in a multi-bit FIFO, the fractured
word configuration is recommended over a cascaded
configuration. For example, 256x36 can be configured as
two blocks of 256x18. This should be taken into account
when building the FIFO blocks manually. However, when
using SmartGen, the user only needs to specify the depth
and width of the necessary FIFO blocks. SmartGen
automatically configures these blocks to optimize
performance.
2-85.
RCLK
WA
RA
Table
shows a logic block diagram of the
2-95.
Table 2-85 on page 2-72
"Timing Characteristics" on
A
describes the
=
EMPTY
v2.7
Overflow and Underflow Control
The counter MSB keeps track of the difference between
the read address (RA) and the write address (WA). The
EMPTY flag is set when the read and write addresses are
equal. To prevent underflow, the write address is double-
sampled by the read clock prior to comparison with the
read address (part A in
the read address is double-sampled by the write clock
prior to comparison to the write address (part B in
Figure
Clock
As with RAM configuration, the RCLK and WCLK pins
have independent polarity selection
Table 2-95 • FIFO Width Configurations
Figure 2-65 • FIFO Block Diagram
WCLK
WIDTH(2:0)
000
001
010
011
100
101
11x
WA
RA
2-64).
DEPTH [3:0]
WIDTH [2:0]
PIPE
FREN
RCLK
AEVAL [7:0]
AFVAL [7:0]
WD [35:0]
FWEN
WCLK
CLR
Figure
B
RD [35:0]
2-64). To prevent overflow,
AEMPTY
EMPTY
Axcelerator Family FPGAs
AFULL
FULL
18 x 256
36 x 128
reserved
=
9 x 512
W x D
1 x 4k
2 x 2k
4 x 1k
FULL
2-83