AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 18

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

P
P
P
P
P
P
P
P
P
2 -4
total
HCLK
CLK
R-cells
C-cells
inputs
outputs
memory
PLL
Axcelerator Family FPGAs
P
P
C
V
po
F
N
F
F
F
F
s
Fs
s
Fs
ms =
Fs
mc = the number of C-cells switching at each Fs cycle
Fs
pi
F
po
RCLK
WCLK
= P13 * F
RefCLK
CLK
dc
ac
pi
CCI
= (P4 + P5 * s + P6 * sqrt[s]) * Fs
load
block
= P
= (P1 + P2 * s + P3 * sqrt[s]) * Fs
= P7 * ms * Fs
= P8 * mc * Fs
= P9 * pi * F
=
= the clock frequency
= the number of inputs
= the average input frequency
=
=
= the number of R-cells clocked by this clock
= the clock frequency
= the number of R-cells clocked by this clock
= the clock frequency
= P
dc
= P11 * N
= the output load (technology dependent)
= the output voltage (technology dependent)
= the number of outputs
= the average output frequency
= the number of RAM/FIFO blocks (1 block = 4k)
= the read-clock frequency of the memory
= the write-clock frequency of the memory
= the clock frequency of the clock input of the PLL
= the clock frequency of the first clock output of the PLL
the number of R-cells switching at each Fs cycle
the clock frequency
+ P
I
P
I/O
CCA
HCLK
CLK
* po * F
ac
* V
+ P
CCA
block
CLK
pi
+ P
po
* F
R-cells
RCLK
+ P
+ P12 * N
C-cells
+ P
inputs
block
+ P
* F
outputs
WCLK
+ P
v2.7
memory
+ P
PLL