DEMO9S08LC60 Freescale Semiconductor, DEMO9S08LC60 Datasheet - Page 169

• Manufacturer Part Number: DEMO9S08LC60
• Description: BOARD DEMO FOR 9S08LC60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S08LC60

• Contents: Evaluation Board
• Processor To Be Evaluated: MC9S08LC60
• Interface Type: RS-232, USB
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08LC
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08LC60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 10
Internal Clock Generator (S08ICGV4)
10.1
The ICG module is used to generate the system clocks for the MC9S08LC60/36/20 MCU.
shows the clock distribution for the MC9S08LC60/36/20 MCU. Electrical parametric data for the ICG
may be found in Appendix.
Figure 10-2
Freescale Semiconductor
ICG
1-kHz
Introduction
ICGLCLK*
ICGERCLK
FFE
shows the MC9S08LC60 Series block diagram with the ICG highlighted.
ICGOUT
* ICGLCLK is the alternate BDC clock source for the MC9S08LC60 Series.
Freescale Semiconductor programs a factory trim value for ICGTRM into
the FLASH location $FFBE (NVICGTRM). Leaving this address for the
ICGTRM value also allows debugger and programmer vendors to perform
a manual trim operation and store the resultant ICGTRM value into
NVICGTRM for users to access at a later time. The value in NVICGTRM
is not automatically loaded and therefore must be copied into ICGTRM by
user code.
CONTROL
CPU
SYSTEM
÷
LOGIC
2
÷
2
FIXED FREQ CLOCK
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
Figure 10-1. System Clock Distribution Diagram
(XCLK)
BUSCLK
RTI
BDC
TPM1
NOTE
LCD
TPM2
COP
TPMCLK
IIC1
Chapter 10 Internal Clock Generator (S08ICGV4)
ADC has min and max
frequency requirements.
See
and the Electricals Appendix.
ADC
SCI
Chapter 1,
“Introduction”
SPI1
RAM
FLASH has frequency
requirements for program
and erase operation.
See the Electricals Appendix.
FLASH
SPI2
Figure 10-1
ACMP
169