DEMO9S08LC60 Freescale Semiconductor, DEMO9S08LC60 Datasheet - Page 189

• Manufacturer Part Number: DEMO9S08LC60
• Description: BOARD DEMO FOR 9S08LC60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S08LC60

• Contents: Evaluation Board
• Processor To Be Evaluated: MC9S08LC60
• Interface Type: RS-232, USB
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08LC
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08LC60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.6.2
In this example, the FLL will be used (in FEE mode) to multiply the external 32 kHz oscillator up to
8.38 MHz to achieve 4.19 MHz bus frequency.
After the MCU is released from reset, the ICG is in self-clocked mode (SCM) and supplies approximately
8 MHz on ICGOUT, which corresponds to a 4 MHz bus frequency (f
The clock scheme will be FLL engaged, external (FEE). So
Solving for N / R gives:
The values needed in each register to set up the desired operation are:
ICGC1 = $38 (%00111000)
ICGC2 = $00 (%00000000)
ICGS1 = $xx
ICGS2 = $xx
ICGFLTLU/L = $xx
Freescale Semiconductor
Bit 7
Bit 6
Bit 5
Bits 4:3 CLKS
Bit 2
Bit 1
Bit 0
Bit 7
Bits 6:4 MFD
Bit 3
Bits 2:0 RFD
This is read only except for clearing interrupt flag
This is read only; should read DCOS = 1 before performing any time critical tasks
Only needed in self-clocked mode; FLT will be adjusted by loop to give 8.38 MHz DCO clock
Bits 15:12 unused
101
110
111
Example #1: External Crystal = 32 kHz, Bus Frequency = 4.19 MHz
HGO
RANGE
REFS
OSCSTEN 0
LOCD
LOLRE
LOCRE
N / R = 8.38 MHz /(32 kHz * 64) = 4 ; we can choose N = 4 and R =1
f
0
0
1
11
0
0
0
000 Sets the MFD multiplication factor to 4
0
000 Sets the RFD division factor to ÷1
0000
ICGOUT
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
14
16
18
Configures oscillator for low power
Configures oscillator for low-frequency range; FLL prescale factor is 64
Oscillator using crystal or resonator is requested
FLL engaged, external reference clock mode
Oscillator disabled
Loss-of-clock detection enabled
Unimplemented or reserved, always reads zero
Generates an interrupt request on loss of lock
Generates an interrupt request on loss of clock
Table 10-12. MFD and RFD Decode Table
= f
ext
* P * N / R ; P = 64, f
ext
101
110
111
= 32 kHz
Chapter 10 Internal Clock Generator (S08ICGV4)
Bus
).
÷128
÷32
÷64
Eqn. 10-1
Eqn. 10-2
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