DEMO9S08LC60 Freescale Semiconductor, DEMO9S08LC60 Datasheet - Page 35

• Manufacturer Part Number: DEMO9S08LC60
• Description: BOARD DEMO FOR 9S08LC60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S08LC60

• Contents: Evaluation Board
• Processor To Be Evaluated: MC9S08LC60
• Interface Type: RS-232, USB
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08LC
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08LC60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.6
One of three stop modes is entered upon execution of a STOP instruction when STOPE in SOPT1 is set.
In any stop mode, the bus and CPU clocks are halted. The ICG module can be configured to leave the
reference clocks running. see
Table 3-1
conditions. The stop mode behavior of the MCU is configured by setting the appropriate bits in the
SPMSC1 and SPMSC2 registers The selected mode is entered following the execution of a STOP
instruction.
3.6.1
Stop3 mode is entered by executing a STOP instruction under the conditions as shown in
states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained.
Stop3 can be exited by asserting RESET, or by an interrupt from one of the following sources: the real-time
interrupt (RTI), LVD, ADC, IRQ or the KBI.
If stop3 is exited by means of the RESET pin, then the MCU is reset and operation will resume after taking
the reset vector. Exit by means of one of the internal interrupt sources results in the MCU taking the
appropriate interrupt vector.
A separate self-clocked source (≈1 kHz) for the real-time interrupt allows a wakeup from stop2 or stop3
mode with no external components. When RTIS2:RTIS1:RTIS0 = 0:0:0, the real-time interrupt function
and this 1-kHz source are disabled. Power consumption is lower when the 1-kHz source is disabled, but in
that case the real-time interrupt cannot wake the MCU from stop.
Freescale Semiconductor
1
2
3
STOPE
ENBDM is located in the BDCSCR which is only accessible through BDC commands, see the
section.
When in Stop3 mode with BDM enabled, The S
The LCD module can operate in stop3 if LCDSTP3 in LCDCR1 is asserted.
0
1
1
1
1
1
Stop Modes
shows all of the control bits that affect stop mode selection and the mode selected under various
Stop3 Mode
ENBDM
1
0
0
0
0
x
1
LVDE and LVDSE
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
Chapter 10, “Internal Clock Generator
x
x
1
0
0
0
Table 3-1. Stop Mode Selection
PDC
x
x
x
0
1
1
IDD
will be near R
PPDC
1
0
x
x
x
x
Stop modes disabled; illegal opcode reset if STOP
instruction executed
Stop3 with BDM enabled
Stop3 with voltage regulator active
Stop3
Stop2
Stop1
IDD
3
levels because internal clocks are enabled.
(S08ICGV4)” for more information.
Stop Mode
2
Chapter 3 Modes of Operation
Development Support
Table
3-1. The
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