M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 15

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION ...............................................668
16.4 Transfer Modes .......................................................................................................................658
16.5 Transfer Types ........................................................................................................................662
16.6 Transfer Target........................................................................................................................662
16.7 DMA Channel Priorities ..........................................................................................................662
16.8 Next Address Setting Function .............................................................................................663
16.9 DMA Transfer Start Factors ...................................................................................................664
16.10 Forcible Termination ..............................................................................................................665
16.11 Times Related to DMA Transfer ............................................................................................666
16.12 Cautions...................................................................................................................................666
16.13 DMA Transfer End...................................................................................................................667
17.1 Features ...................................................................................................................................668
17.2 Non-Maskable Interrupts........................................................................................................672
17.3 Maskable Interrupts ................................................................................................................677
17.4 External Interrupt Request Input Pins (INTP0 to INTP7).....................................................692
17.5 Software Exception.................................................................................................................695
17.6 Exception Trap ........................................................................................................................698
17.7 Multiple Interrupt Servicing Control .....................................................................................702
17.8 Interrupt Response Time of CPU ..........................................................................................704
17.9 Periods in Which CPU Does Not Acknowledge Interrupts .................................................705
17.10 Caution.....................................................................................................................................705
16.3.3 DMA transfer count registers 0 to 3 (DBC0 to DBC3)................................................................. 649
16.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3) .................................................... 650
16.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3)......................................................... 652
16.3.6 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) .............................................................. 654
16.4.1 Single transfer mode .................................................................................................................. 658
16.4.2 Single-step transfer mode........................................................................................................... 660
16.4.3 Block transfer mode.................................................................................................................... 661
16.5.1 2-cycle transfer ........................................................................................................................... 662
16.6.1 Transfer type and transfer target ................................................................................................ 662
17.2.1 Operation.................................................................................................................................... 673
17.2.2 Restore ....................................................................................................................................... 675
17.2.3 Non-maskable interrupt status flag (NP)..................................................................................... 676
17.3.1 Operation.................................................................................................................................... 677
17.3.2 Restore ....................................................................................................................................... 679
17.3.3 Priorities of maskable interrupts ................................................................................................. 680
17.3.4 Interrupt control registers (xxICn) ............................................................................................... 684
17.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3)........................................................................... 688
17.3.6 In-service priority register (ISPR)................................................................................................ 690
17.3.7 Maskable interrupt status flag (ID).............................................................................................. 691
17.4.1 Noise elimination ........................................................................................................................ 692
17.4.2 Edge detection............................................................................................................................ 693
17.5.1 Operation.................................................................................................................................... 695
17.5.2 Restore ....................................................................................................................................... 696
17.5.3 Exception status flag (EP) .......................................................................................................... 697
17.6.1 Illegal opcode definition .............................................................................................................. 698
17.6.2 Debug trap.................................................................................................................................. 700
User’s Manual U16543EJ4V0UD
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