M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 444

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

442
Cautions 1. Set the value “M” of the TQnCCR0 register in a range of 0002H ≤ M ≤ FFFEH in the 6-phase
Remark
(internal signal)
(internal signal)
(internal signal)
pin output (W)
pin output (W)
TOQn1 signal
TOQn2 signal
TOQn3 signal
pin output (U)
pin output (U)
pin output (V)
pin output (V)
2. Only a value of up to “M + 1” can be set to the TQnCCR1, TQnCCR2, and TQnCCR3
3. The output is 100% if “0000H” is set to the TQnCCR1, TQnCCR2, and TQnCCR3 registers.
4. If the operation value of an equation (such as (M + 1 – i) × 2 – N) of the output width of
V850E/IA3: n = 0
Dead-time
Dead-time
Dead-time
TQnCCR0
TQnCCR1
TQnCCR2
TQnCCR3
pin output
counter 1
counter 2
counter 3
TQnDTC
TOQnB1
TOQnB2
TOQnB3
TOQnT1
TOQnT2
TOQnT3
counter
register
register
register
register
register
TOQn0
PWM output mode.
registers.
The output is 0% if “M + 1” is set to the TQnCCR1, TQnCCR2, and TQnCCR3 registers.
The output (duty 50%) rises at the crest (M + 1) of the 16-bit counter and falls at the valley
(0000H) if “M + 2” or higher is set to the TQnCCR1, TQnCCR2, and TQnCCR3 registers.
phases U, V, and W is 0 or lower, it is converged to 0 (100% output). If the operation value
is higher than “(M + 1) × 2”, it is converged to (M + 1) × 2 (0% output).
0000H
16-bit
M (carrier data)
i (phase U data)
j (phase V data)
k (phase W data)
N (dead-time value)
i
Figure 10-6. Timing Chart of 6-Phase PWM Output Mode
j
V850E/IA4: n = 0, 1
CHAPTER 10 MOTOR CONTROL FUNCTION
k
M + 1
User’s Manual U16543EJ4V0UD
k
Basic phase W output width = (M + 1
Phase W output width = (M + 1
Phase W output width = (M + 1
j
Phase V output width = (M + 1
Basic phase V output width = (M + 1
Phase V output width = (M + 1
i
Phase U output width = (M + 1
Basic phase U output width = (M + 1
Phase U output width = (M + 1
Dead-time width = N
Carrier cycle = (M + 1)
i
−
k)
−
×
j
−
k)
2
k)
−
×
−
×
N
j)
2 + N
2
×
−
2
k
−
j)
×
−
j)
×
−
2
N
M + 1
×
2 + N
i)
2
×
−
2
−
i)
−
i)
×
k
N
×
2 + N
2
j
i