M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 252

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M-V850E-IA4

Manufacturer Part Number
M-V850E-IA4
Description
KIT EVAL V850E IA4 UPD70F3186
Manufacturer
Renesas Electronics America
Datasheets

Specifications of M-V850E-IA4

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
250
(c) Generation timing of compare match interrupt request signal (INTTPmCC1)
INTTPmCC1 signal
TPmCCR1 register
TOPm1 pin output
The timing of generation of the INTTPmCC1 signal in the PWM output mode differs from the timing of
INTTPmCC1 signals in other modes; the INTTPmCC1 signal is generated when the count value of the 16-
bit counter matches the value of the TPmCCR1 register.
Note Actually, the timing is delayed by one operating clock (f
Remark
Usually, the INTTPmCC1 signal is generated in synchronization with the next counting up after the count
value of the 16-bit counter matches the value of the TPmCCR1 register.
In the PWM output mode, however, it is generated one clock earlier. This is because the timing is changed
to match the change timing of the output signal of the TOPm1 pin.
16-bit counter
Count clock
V850E/IA3: m = 0, 2
V850E/IA4: m = 0, 2, 3
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
D
1
− 2
User’s Manual U16543EJ4V0UD
D
1
− 1
Note
Note
D
D
1
1
XX
).
D
1
+ 1
D
1
+ 2

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