M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 172

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.5.2
170
Internal reset signal
(1) Power on (power-on reset)
Cautions 1. The clock generated by the oscillator starts oscillating during the RESET period.
PLL output clock
RESET (input)
<1> The oscillator is activated during the RESET period that follows power application.
<2> When the fixed oscillation stabilization time that elapses after the RESET signal is released expires,
<3> PLL is locked when counting of the lockup time is over. The OST counter is initialized to 00H.
<4> When the lockup time expires, the CPU releases the reset signal and operates in the clock-through
Operation timing
OST counter
Make sure that the low-level width of the RESET signal is “Oscillation stabilization time of the
resonator − Fixed oscillation stabilization time” or more, taking the oscillation stabilization time into
consideration.
PLL stops during the RESET period and fixed oscillation stabilization time.
PLL stop is released, and counting the lockup time starts.
mode (f
2. To avoid malfunction due to noise, do not change the division ratio of the CPU operation
V
f
CPU
X1
After the RESET signal is released, a specific wait time (fixed oscillation stabilization time)
elapses.
clock (f
division ratio, be sure to select the PLL mode.
DD
X
). The CPU operation clock (f
CPU
00H (initialization)
Oscillation stabilization time
) by using the PCC register before setting the PLL mode. Before changing the
<1>
CHAPTER 5 CLOCK GENERATOR
Fixed oscillation stabilization
time of clock from oscillator
User’s Manual U16543EJ4V0UD
1.024 ms (8 MHz)
CPU
) is f
XX
/8. The PLL mode can be set by software.
1.024 ms (8 MHz)
PLL lockup time
<2>
f
XX
/8 of clock-through mode after RESET
<3>
PLL output stabilized
00H
<4>