M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 285

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(4) TMQ0 I/O control register 1 (TQ0IOC1)
Cautions 1. Rewrite the TQ0IS7 to TQ0IS0 bits when the TQ0CTL0.TQ0CE bit = 0. (The same value can
The TQ0IOC1 register is an 8-bit register that controls the valid edge for the capture trigger input signals
(TIQ00 to TIQ03 pins).
This register can be read or written in 8-bit or 1-bit units.
Rest sets this register to 00H.
Remark
2. The TQ0IS7 to TQ0IS0 bits are valid only in the free-running timer mode (only when
TQ0IOC1
be written when the TQ0CE bit = 1.) If rewriting was mistakenly performed, clear (0) the
TQ0CE bit and then set the bits again.
TQ0OPT0.TQ0CCS3 to TQ0OPT0.TQ0CCS0 bits = 1111) and pulse width measurement
mode. In all other modes, a capture operation is not performed.
TMQ1 does not have the TQ1IOC1 register.
After reset: 00H
TQ0IS7
TQ0IS5
TQ0IS3
TQ0IS1
TQ0IS7
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
7
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ)
TQ0IS6
TQ0IS4
TQ0IS2
TQ0IS0
R/W
TQ0IS6
6
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Address: FFFFF5C3H
User’s Manual U16543EJ4V0UD
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
TQ0IS5
Capture trigger input signal (TIQ03 pin) valid edge setting
Capture trigger input signal (TIQ02 pin) valid edge setting
Capture trigger input signal (TIQ01 pin) valid edge setting
Capture trigger input signal (TIQ00 pin) valid edge setting
5
TQ0IS4
4
TQ0IS3
3
TQ0IS2
2
TQ0IS1
1
TQ0IS0
0
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