M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 225

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

<R>
<R>
16-bit counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from
the TOPm1 pin. If the trigger is generated again while the counter is operating, the counter is cleared to 0000H and
restarted. (The output of the TOP00 pin is inverted. The TOPm1 pin outputs high level regardless of the status
(high/low) when a trigger occurs.)
after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The
compare match interrupt request signal INTTPmCC1 is generated when the count value of the 16-bit counter matches
the value of the CCR1 buffer register.
bit counter matches the value of the CCRa buffer register and the 16-bit counter is cleared to 0000H.
used as the trigger.
16-bit timer/event counter P waits for a trigger when the TPmCE bit is set to 1. When the trigger is generated, the
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
The compare match interrupt request signal INTTPmCC0 is generated when the 16-bit counter counts next time
The value set to the TPmCCRa register is transferred to the CCRa buffer register when the count value of the 16-
The valid edge of an external trigger input (TIPk0) or setting the software trigger (TPmCTL1.TPmEST bit) to 1 is
Remark
External trigger input
INTTPmCC0 signal
INTTPmCC1 signal
TPmCCR0 register
TPmCCR1 register
TOPm1 pin output
Active level width = (Set value of TPmCCR1 register) × Count clock cycle
Cycle = (Set value of TPmCCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TPmCCR1 register)/(Set value of TPmCCR0 register + 1)
TOP00 pin output
(only when using
(TIPk0 pin input)
software trigger)
16-bit counter
TPmCE bit
V850E/IA3: m = 0, 2, k = 0, 2, a = 0, 1
V850E/IA4: m = 0, 2, 3, k = 0, 2, a = 0, 1
FFFFH
0000H
Figure 6-24. Basic Timing in External Trigger Pulse Output Mode
trigger
Wait
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
for
Active level
width (D
Cycle (D
D
1
1
)
D
0
User’s Manual U16543EJ4V0UD
0
+ 1)
Active level
width (D
Cycle (D
D
1
1
)
D
0
0
+ 1)
D
D
0
1
D
1
D
0
Active level
width (D
Cycle (D
D
1
1
)
D
0
0
+ 1)
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