M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 438

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

436
Notes 1. V850E/IA4 only
2. • V850E/IA3
3. When using the comparator output, set the rising edge input.
HZAmCTLn
V850E/IA3
V850E/IA4
m = 0 to 2
• V850E/IA4
After reset: 00H
m = 0, 2
n = 0, 1
n = 0, 1
HZA0CTL0: TOQ0OFF pin,
HZA2CTL0: ANI00, ANI01 pins,
HZA0CTL0: TOQ0OFF pin,
HZA1CTL0: TOQ1OFF pin,
HZA2CTL0: ANI00 to ANI02 pins, HZA2CTL1: ANI10 to ANI12 pins
HZAmDCEn
HZAmDCEn
HZAmDCMn
HZAmDCNn
Rewrite the HZAmDCMn bit when the HZAmDCEn bit = 0.
• Rewrite the HZAmDCNn and HZAmDCPn bits when the HZAmDCEn bit is 0.
• For the edge specification of the INTP0 to INTP3 pins, see 17.4.2 (1) External
• The edge of the external pins must be specified starting from the TOQnOFF and
• High-impedance output control is performed when the valid edge is input after the
interrupt rising edge specification register 0 (INTR0), external interrupt
falling edge specification register 0 (INTF0).
TOPmOFF pins. Then the edge of the external pins other than the TOQnOFF and
TOPmOFF pins must be specified. Otherwise, the undefined edge may be
detected when the edges of the TOQnOFF and TOPmOFF pins are specified.
operation is enabled (by setting HZAmDCEn bit to 1). If the external pin
the active level when the operation is enabled, therefore, high-impedance output
control is not performed.
<7>
0
1
0
1
0
0
1
1
R/W
HZAmDCMn HZAmDCNn HZAmDCPn HZAmDCTn HZAmDCCn
Disable high-impedance output control operation. Pins can function as
output pins.
Enable high-impedance output control operation.
Setting of the HZAmDCCn bit is valid regardless of the external pin
input.
Setting of the HZAmDCCn bit is invalid while the external pin
holds a level detected as abnormal (active level).
HZAmDCPn
CHAPTER 10 MOTOR CONTROL FUNCTION
<6>
0
1
0
1
Condition of clearing high-impedance state by HZAmDCCn bit
Address: HZA0CTL0 FFFFF5F0H, HZA0CTL1 FFFFF5F1H,
No valid edge (setting the HZAmDCFn bit by external pin
input is prohibited).
Rising edge of the external pin
(abnormality is detected by rising edge input)
Falling edge of the external pin
(abnormality is detected by falling edge input).
Setting prohibited
User’s Manual U16543EJ4V0UD
5
HZA0CTL1: TOP2OFF pin,
HZA2CTL1: ANI10 to ANI12 pins
HZA0CTL1: TOP2OFF pin,
HZA1CTL1: TOP3OFF pin,
HZA1CTL0 FFFFF630H
HZA2CTL0 FFFFF638H, HZA2CTL1 FFFFF639H
External pin
High-impedance output control
4
Note 2
<3>
input edge specification
Note 2
Note 2
Note 1
<2>
input is valid
input is valid
, HZA1CTL1 FFFFF631H
Note 3
1
0
.
Note 2
Note 2
HZAmDCFn
input
Note 2
<0>
Note 2
is at
Note 1
,
(1/2)