M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 307

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

<R>
<R>
with the count clock, and the counter starts counting. At this time, the output of the TOQn0 pin
Additionally, the set value of the TQnCCR0 register is transferred to the CCR0 buffer register.
cleared to 0000H, the output of the TOQn0 pin
(INTTQnCC0) is generated.
TQnCTL1
TQnCTL0
When the TQnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is
The interval can be calculated by the following expression.
Interval = (Set value of TQnCCR0 register + 1) × Count clock cycle
Note The TOQ10 pin is provided only in the V850E/IA4.
Remark
(a) TMQn control register 0 (TQnCTL0)
(b) TMQn control register 1 (TQnCTL1)
Note Enable setting of the TQ0EEE bit to 1 only when timer output (TOQ00, TOQ0b) is used.
TQnCE
n = 0, 1
0/1
0
In this case, set the TQ0CCR0 and TQ0CCRb registers to the same value (b = 1 to 3).
TQ0EST
Figure 7-9. Register Setting for Interval Timer Mode Operation (1/3)
0
0
TQ0EEE
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ)
0/1
0
Note
0
0
User’s Manual U16543EJ4V0UD
Note
0
0
is inverted, and a compare match interrupt request signal
TQnCKS2 TQnCKS1 TQnCKS0
TQnMD2 TQnMD1 TQnMD0
0/1
0
0/1
0
0/1
0
0, 0, 0:
Interval timer mode
Select count clock
0: Stop counting
1: Enable counting
0: Operate on count
1: Count with external
clock selected by
TQ0CKS0 to TQ0CKS2 bits
event count input signal
Note
is inverted.
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