M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 191

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 6-4. Function of Capture/Compare Register in Each Mode and How to Write Compare Register
Interval timer
External event counter
External trigger pulse output
One-shot pulse output
PWM output
Free-running timer
Pulse width measurement
(a) Function as compare register
(b) Function as capture register (TP0CCR0 and TP2CCR0 registers only)
The following table shows the functions of the capture/compare register in each mode, and how to write data to
the compare register.
Notes 1. TMP0 and TMP2 only
Remark
The TPnCCR0 register can be rewritten even when the TPnCTL0.TPnCE bit = 1.
The set value of the TPnCCR0 register is transferred to the CCR0 buffer register. When the value of the
16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal
(INTTPnCC0) is generated. If TOP00 pin output is enabled at this time, the output of the TOP00 pin is
inverted (TOP10, TOP20, and TOP30 pins are not provided).
When the TPnCCR0 register is used as a cycle register in the interval timer mode, external event count
mode, external trigger pulse output mode, one-shot pulse output mode, or PWM output mode, the value of
the 16-bit counter is cleared (0000H) if its count value matches the value of the CCR0 buffer register.
The compare register is not cleared by the TPnCTL0.TPnCE bit = 0.
When the TPkCCR0 register is used as a capture register in the free-running timer mode, the count value
of the 16-bit counter is stored in the TPkCCR0 register if the valid edge of the capture trigger input pin
(TIPk0 pin) is detected. In the pulse width measurement mode, the count value of the 16-bit counter is
stored in the TPkCCR0 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture
trigger input pin (TIPk0 pin) is detected.
Even if the capture operation and reading the TPkCCR0 register conflict, the correct value of the TPkCCR0
register can be read.
The capture register is cleared by the TPkCTL0.TPkCE bit = 0.
Remark
2. TMP0 and TMP2 only (also TMP3 in software trigger mode in the V850E/IA4)
3. TMP0 and TMP2 only (also TMP3 in the V850E/IA4)
4. Writing to the TPnCCR1 register is the trigger.
Operation Mode
Note 3
For anytime write and batch write, see 6.6 (2) Anytime write and batch write.
k = 0, 2
Note 2
Note 1
Note 1
Note 2
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
Compare register
Compare register
Compare register
Compare register
Compare register
Capture/compare register
Capture register
User’s Manual U16543EJ4V0UD
Capture/Compare Register
Anytime write
Anytime write
Batch write
Anytime write
Batch write
Anytime write
None
How to Write Compare Register
Note 4
Note 4
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