M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 532

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.6 Operation in Timer Trigger Modes 0 and 1
(TQTADTn0, TQTADTn1) from the timer (motor control function) (see Figure 12-3).
(TQaOPT2) and the TQaAT10 to TQaAT13 bits of TMQa option register 3 (TQaOPT3). The trigger sources of the
motor control function that can be selected as the A/D conversion start trigger, which is a timer trigger, are the
INTTPaCC0, INTTPaCC1, INTTQaCC0, and INTTQaOV signals (two or more signals can be selected).
rising edge of the A/D conversion start trigger signal (TQTADTa0, TQTADTa1) selected for the motor control function.
trigger signal is input, it starts A/D conversion.
and, at the same time, the A/Dn conversion end interrupt request signal (INTADn) is generated.
ADAnM0.ADAnMD1 and ADAnM0.ADAnMD0 bits.
converter is waiting for a trigger, the ADAnM0.ADAnEF bit = 0 (conversion stopped).
beginning. If the ADAnM0, ADAnM2, and ADAnS registers are written during A/D conversion, the conversion is
stopped and the A/D converter waits for a trigger again.
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With A/D converter n, the conversion timing is specified by using the A/D conversion start trigger signal
• Timer trigger of A/D converter 0
• Timer trigger of A/D converter 1
The TQTADTa0 and TQTADTa1 signals are set by using the TQaAT00 to TQaAT03 bits of TMQa option register 2
When the ADAnM2.ADAnTMD1 and ADAnM2.ADAnTMD0 bits are set to 01 or 10, A/D conversion is started at the
When the ADAnM0.ADAnCE bit is set to 1, the A/D converter waits for a trigger and, when the A/D conversion start
After the end of A/D conversion, the conversion result is stored in A/Dn conversion result register m (ADAnCRm)
After the end of A/D conversion, the A/D converter waits for a trigger regardless of the operation mode set by the
When conversion is started, the ADAnM0.ADAnEF bit is set to 1 (conversion in progress). However, while the A/D
If a valid trigger is input during A/D conversion, the conversion operation is stopped and started again from the
Caution In timer trigger modes 0 and 1, make sure that the A/D conversion start trigger signal (A/D
Remark
In timer trigger mode 0: TQTADT00
In timer trigger mode 1: TQTADT10 (V850E/IA4 only)
In timer trigger mode 0: TQTADT01
In timer trigger mode 1: TQTADT11 (V850E/IA4 only)
conversions start timing) is not generated at an interval shorter than the minimum number of
conversion clocks that can be specified by the ADAnM1.ADAnFR1 and ADAnM1.ADAnFR0 bits.
If the A/D conversion start trigger signal is generated at an interval shorter than the minimum
number of conversion clocks, the last trigger is valid.
n = 0, 1
m = 0 to 3
V850E/IA3: a = 0
V850E/IA4: a = 0, 1
CHAPTER 12 A/D CONVERTERS 0 AND 1
User’s Manual U16543EJ4V0UD