M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 237

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M-V850E-IA4

Manufacturer Part Number
M-V850E-IA4
Description
KIT EVAL V850E IA4 UPD70F3186
Manufacturer
Renesas Electronics America
Datasheets

Specifications of M-V850E-IA4

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
<R>
6.6.4
is set to 1. When the valid edge of an external trigger input (TIPk0) is detected, 16-bit timer/event counter P starts
counting, and outputs a one-shot pulse from the TOPm1 pin.
trigger is used, the TOP00 pin outputs the active level while the 16-bit counter is counting, and the inactive level when
the counter is stopped (waiting for a trigger).
This mode is valid only in TMP0, TMP2, and TMP3 (V850E/IA4 only) (software trigger only for TMP3).
In the one-shot pulse output mode, 16-bit timer/event counter P waits for a trigger when the TPmCTL0.TPmCE bit
Instead of the external trigger, a software trigger can also be generated to output the pulse. When the software
(external trigger input)
One-shot pulse output mode (TPmMD2 to TPmMD0 bits = 011)
Note Because the external trigger input pin (TIP00) and timer output pin (TOP00) function alternately,
Caution In the one-shot pulse output mode, select the internal clock as the count clock (by
Remark
TIPk0 pin
two functions cannot be used at the same time.
Note
clearing the TPkCTL1.TPkEEE bit to 0).
V850E/IA3: m = 0, 2, k = 0, 2
V850E/IA4: m = 0, 2, 3, k = 0, 2
Software trigger
Figure 6-27. Configuration in One-Shot Pulse Output Mode
selection
generation
Count
clock
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
detector
Edge
TPmCE bit
User’s Manual U16543EJ4V0UD
control
Count
start
CCR1 buffer register
CCR0 buffer register
TPmCCR1 register
TPmCCR0 register
16-bit counter
Match signal
Match signal
Clear
Transfer
Transfer
S
R
S
R
controller
controller
(RS-FF)
(RS-FF)
Output
Output
INTTPmCC1 signal
INTTPmCC0 signal
TOPm1 pin
TOP00 pin
Note
235

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