M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 566

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.4.3 Operation timing
564
A/D2 conversion result
register n (ADA2CRn)
The operation timing in each buffer mode and operation mode is shown below.
(1) 1-buffer serial mode
Figure 13-4. Example of Operation Timing in 1-Buffer Serial Mode (with 8-Bit Resolution, f
Remarks 1. Data:
INTAD2 interrupt
Notes 1. The ANI26 and ANI27 pins are only available in the V850E/IA4.
A/D conversion of the analog input pin (ANI2n)
conversion result is continuously stored in A/D2 conversion result register n (ADA2CRn) corresponding to the
ANI2n pin (n = 0 to 7).
The ANI2n pin and the ADA2CRn register correspond one to one (see Table 13-2).
Each time A/D conversion ends, the A/D2 conversion end interrupt request signal (INTAD2) is generated.
After conversion has ended once, it is repeated with the same ANI2n pin
bit is cleared to 0 (conversion stopped).
It is not required to set (1) the ADA2CTL0.ADA2CE bit to restart A/D conversion
Conversion can be stopped by clearing the ADA2CE bit to 0.
ADA2CE bit
DF counter
2. In 1-buffer serial mode, unless the ADA2CTL0.ADA2CE bit is cleared to 0, A/D conversion is not
3. f
2. n = 0 to 7
stopped. Therefore, the contents of the ADA2CRn register must be read before A/D conversion
ends, or the register is overwritten (n = 0 to 7).
DF counter: Digital filter
When the ANI2n pin is selected, the result of conversion is stored in the ADA2CRn register.
XX
: Peripheral clock
128 s + 6 clocks
μ
Data 0
Conversion data
CHAPTER 13 A/D CONVERTER 2
128 s
Data 1
Data 0
User’s Manual U16543EJ4V0UD
μ
Note 1
Data 2
Data 1
specified by the ADA2CTL2 register is executed, and the
Data 3
Data 2
Note 1
, unless the ADA2CTL0.ADA2CE
Note 2
.
Data 4
Data 3
XX
= 64 MHz)
Data 5
Data 4