M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 254

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

252
• Compare operation
When the TPnCE bit is set to 1, 16-bit timer/event counter P starts counting, and the output signals of the TOP00
and TOPm1 pins are inverted. When the count value of the 16-bit counter later matches the set value of the
TPnCCRa register, a compare match interrupt request signal (INTTPnCCa) is generated, and the output signals
of the TOP00 and TOPm1 pins are inverted.
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
generates an overflow interrupt request signal (INTTPnOV) at the next clock, is cleared to 0000H, and continues
counting. At this time, the overflow flag (TPnOPT0.TPnOVF bit) is also set to 1. Confirm that the overflow flag is
set to 1 and then clear it to 0 by executing the CLR instruction via software.
The TPnCCRa register can be rewritten while the counter is operating. If it is rewritten, the new value is reflected
at that time by anytime write, and compared with the count value.
INTTPnCC0 signal
INTTPnCC1 signal
TPnCCR0 register
TPnCCR1 register
TOPm1 pin output
TOP00 pin output
INTTPnOV signal
Remark
16-bit counter
TPnOVF bit
TPnCE bit
Figure 6-36. Basic Timing in Free-Running Timer Mode (Compare Function)
FFFFH
0000H
V850E/IA3: n = 0 to 3, m = 0, 2, a = 0, 1
V850E/IA4: n = 0 to 3, m = 0, 2, 3, a = 0, 1
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
D
10
D
00
D
User’s Manual U16543EJ4V0UD
10
CLR instruction
Cleared to 0 by
D
00
D
10
D
00
Cleared to 0 by
CLR instruction
D
11
D
01
CLR instruction
Cleared to 0 by
D
11
D
D
D
01
01
11
Cleared to 0 by
CLR instruction
D
11