M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 415

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M-V850E-IA4

Manufacturer Part Number
M-V850E-IA4
Description
KIT EVAL V850E IA4 UPD70F3186
Manufacturer
Renesas Electronics America
Datasheets

Specifications of M-V850E-IA4

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
8.6.3 Interrupt request signal output upon compare match
CM1n1, CC1n0
match of the TMENC1n count value and the set value of the corresponding compare register.
8.6.4 TM1UBDn flag (bit 0 of STATUS1n register) operation
up/count down operation at every internal operation clock.
CHAPTER 8 16-BIT 2-PHASE ENCODER INPUT UP/DOWN COUNTER/GENERAL-PURPOSE TIMER (TIMER ENC1n)
An interrupt request signal is output when the count value of TMENC1n matches the set value of the CM1n0,
Note When the CC1n0 and CC1n1 registers are set to the compare register mode.
An interrupt request signal such as the one illustrated in Figure 8-15 is output at the next count clock following a
In the UDC mode (TUM1n.CMDn bit = 1), the TM1UBDn flag changes as follows during a TMENC1n count
Remark
(CM1n1 with Operation Mode Set to General-Purpose Timer Mode and Count Clock Set to f
f
XX
Note
: Peripheral clock
, or CC1n1
Figure 8-15. Interrupt Request Signal Output upon Compare Match
Internal match signal
TM1UBDn flag
Note
CM1n1 register
Count clock
TMENC1n
register. The interrupt generation timing is as follows.
Count clock
TMENC1n
INTCMn1
Figure 8-16. TM1UBDn Flag Operation
f
XX
0000H
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User’s Manual U16543EJ4V0UD
0007H
0001H
0008H
0000H
0009H
0009H
0001H
000AH
0000H
000BH
0001H
XX
/4)
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