M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 545

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

<R>
12.9.8 Restrictions on setting one-shot mode and software trigger mode
1010XX0XB) or one-shot scan mode and software trigger mode (ADAnM0 register = 1011XX0XB), a re-conversion
operation should be performed in a new condition when data is written to any of the ADAnM0, ADAnM2, and ADAnS
registers upon completion of an A/D conversion operation. However, the re-conversion operation is not performed but
the conversion operation is enabled (ADAnM0.ADAnCE bit = 1) and stopped (ADAnM0.ADAnEF bit = 0). The A/Dn
conversion end interrupt request signal (INTADn) is not generated, nor is the last A/D conversion result stored.
However, the data is correctly written to any of the ADAnM0, ADAnM2, and ADAnS registers.
written to the ADAnM0 register upon completion of an A/D conversion operation in the one-shot scan mode and
software trigger mode (ADAnM0 register = 1011XX0XB), the signal of the ANIn0 pin is correctly converted and the
conversion result is correctly stored in the ADAnCR0 register. However, the result of converting the signal of the
ANIn1 pin which has been performed immediately before the completion of the A/D conversion is not stored in the
ADAnCR1 register, nor is the INTADn interrupt request signal generated.
If the A/D converters 0 and 1 are set in the one-shot select mode and software trigger mode (ADAnM0 register =
If this happens, normal operation can be restored by setting the ADAnM0.ADAnCE bit to 1.
For example, if the ANIn0 and ANIn1 pins are set in the scan mode (ADAnS register = 00000001B) and data is
[Countermeasure]
<1> Before writing to any of the ADAnM0, ADAnM2, and ADAnS registers, confirm that A/D conversion is
<2> After disabling the interrupt (PSW.ID bit = 1) or disabling the DMA transfer (DCHCn.Enn bit = 0), execute an
<3> Disable the A/D conversion operation by clearing the ADAnCE bit to 0, write data to any of the ADAnM0,
The above restriction can be avoided by performing any of steps <1> to <3>, below.
stopped (ADAnM0.ADAnEF bit = 0).
instruction that writes data to any of the ADAnM0, ADAnM2, and ADAnS registers and an instruction that
sets the ADAnM0.ADAnCE bit to 1 consecutively, and then enable the interrupt (PSW.ID bit = 0) or enable
the DMA transfer (DCHCn.Enn bit = 1).
This action is to avoid coincidence between the completion of the A/D conversion operation and writing to the
ADAnM0, ADAnM2, or ADAnS register. If, for example, executing a write instruction and the completion of
the A/D conversion operation coincide and thus the A/D conversion is stopped, the A/D conversion can be
started by setting of the ADAnCE bit to 1. If the ADAnM0.ADAnCE bit = 1, the ADAnCE bit is set to 1 again
consecutively.
ADAnM2, and ADAnS registers, enable the A/D conversion operation by setting the ADAnCE bit to 1, and
start the A/D conversion.
CHAPTER 12 A/D CONVERTERS 0 AND 1
User’s Manual U16543EJ4V0UD
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