M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 242

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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240
(2) Operation timing in one-shot pulse output mode
External trigger input
INTTPmCC0 signal
INTTPmCC1 signal
TPmCCR0 register
TPmCCR1 register
TOPm1 pin output
TOP00 pin output
(a) Note on rewriting TPmCCRa register
(only when using
(TIPk0 pin input)
software trigger)
16-bit counter
If the value of the TPmCCRa register is rewritten to a smaller value during counting, the 16-bit counter may
overflow. When an overflow may occur, stop counting and then change the set value.
When the TPmCCR0 register is rewritten from D
D
greater than D
greater than D
and compared with the count value. The counter counts up to FFFFH and then counts up again from
0000H. When the count value matches D
TOPm1 pin. When the count value matches D
the TOPm1 pin, and stops counting.
Therefore, the counter may output a pulse with a delay period or active period different from that of the
one-shot pulse that is originally expected.
Remark
TPmCE bit
00
> D
FFFFH
0000H
01
and D
V850E/IA3: m = 0, 2, k = 0, 2, a = 0, 1
V850E/IA4: m = 0, 2, 3, k = 0, 2, a = 0, 1
01
11
10
and less than D
and less than D
> D
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
11
, if the TPmCCR1 register is rewritten when the count value of the 16-bit counter is
Delay
(D
10
D
)
10
Active level width
(D
00
00
User’s Manual U16543EJ4V0UD
10
, each set value is reflected as soon as the register has been rewritten
D
− D
00
and if the TPmCCR0 register is rewritten when the count value is
10
+ 1)
D
11
10
, the counter generates the INTTPmCC1 signal and asserts the
D
01
Delay
(D
00
, the counter generates the INTTPmCC0 signal, deasserts
00
10
D
)
10
to D
Active level width
(D
00
01
D
− D
00
and the TPmCCR1 register from D
10
+ 1)
D
10
Delay
(10000H + D
D
00
11
)
D
D
D
Active level width
(D
11
11
01
D
01
01
− D
10
11
to D
+ 1)
11
where