M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 407

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.5.2 Operation in UDC mode
CHAPTER 8 16-BIT 2-PHASE ENCODER INPUT UP/DOWN COUNTER/GENERAL-PURPOSE TIMER (TIMER ENC1n)
(1) Overview of operation in UDC mode
The count clock input to TMENC1n in the UDC mode (TUM1n.CMDn bit = 1) can only be externally input from
the TIUD1n and TCUD1n pins. Up/count down judgment in the UDC mode is determined based on the phase
difference of the TIUD1n and TCUD1n pin inputs according to the PRM1n register setting (there is a total of
four choices).
The UDC mode is further divided into two modes according to the TMENC1n clear conditions (a count
operation is performed only with TIUD1n and TCUD1n input in both modes).
• UDC mode A (TUM1n.CMDn bit = 1, MSELn bit = 0)
• UDC mode B (TUM1n.CMDn bit = 1, MSELn bit = 1)
PRM1n2
The TMENC1n clear source can be selected as only external clear input (TCLR1n), the signal indicating a
match between the TMENC1n count value and the CM1n0 register set value during an count up operation,
or the logical sum (OR) of the two signals, using the TMC1n.CLRn1 and TMC1n.CLRn0 bits.
TMENC1n can transfer the value of the CM1n0 register upon occurrence of a TMENC1n underflow.
The status of TMENC1n after a match of the TMENC1n count value and the CM1n0 register set value is as
follows.
<1> In the case of an count up operation, TMENC1n is cleared (0000H), and the INTCMn0 interrupt
<2> In the case of a count down operation, the TMENC1n count value is decremented (−1).
The status of TMENC1n after a match of the TMENC1n count value and the CM1n1 register set value is as
follows.
<1> In the case of an count up operation, the TMENC1n count value is incremented (+1).
<2> In the case of a count down operation, TMENC1n is cleared (0000H), and the INTCMn1 interrupt
1
1
1
1
request signal is generated.
request signal is generated.
PRM1n Register
PRM1n1
0
0
1
1
PRM1n0
Table 8-4. List of Count Operations in UDC Mode
0
1
0
1
Operation
Mode 1
Mode 2
Mode 3
Mode 4
Mode
User’s Manual U16543EJ4V0UD
Count down when TCUD1n = high level
Count up when TCUD1n = low level
Count up upon detection of valid edge of TIUD1n input
Count down upon detection of valid edge of TCUD1n input
Count up upon detection of valid edge of TIUD1n input when
TCUD1n = high level
Count down upon detection of valid edge of TIUD1n input
when TCUD1n = low level
Automatic judgment upon detection of both edges of
TIUD1n input and both edges of TCUD1n input
TMENC1n Operation
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