XC4VFX12-10SFG363C Xilinx Inc, XC4VFX12-10SFG363C Datasheet - Page 101

• Manufacturer Part Number: XC4VFX12-10SFG363C
• Description: IC FPGA VIRTEX-4 FX 12K 363FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-10SFG363C

• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Total Ram Bits: 663552
• Number Of I /o: 240
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 363-FBGA, FCBGA
• Package: 363FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 12312
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 240
• Ram Bits: 663552
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

PMCD Primitives, Ports, and Attributes
Table 3-2: PMCD Port Description
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
CLKA
CLKB
CLKC
CLKD
RST
REL
CLKA1
CLKA1D2
CLKA1D4
CLKA1D8
CLKB1
CLKC1
CLKD1
Port Name
R
Direction
Output
Output
Output
Output
Output
Input
Input
Input
Input
Figure 3-2
includes an example of a PMCD instantiation template.
Table 3-2
CLKA is a clock input to the PMCD. The CLKA frequency can be divided by 1, 2, 4, and 8.
CLKB, CLKC, and CLKD are clock inputs to the PMCD. These clock are not divided by the
PMCD; however, they are delayed by the PMCD to maintain the phase alignment and phase
relationship at the input clocks.
RST is the reset input to the PMCD. Asserting the RST signal asynchronously forces all
outputs Low. Deasserting RST synchronously allows all outputs to toggle.
REL is the release input to the PMCD. Asserting the REL signal releases the divided output
synchronous to CLKA.
The CLKA1 output has the same frequency as the CLKA input. It is a delayed version of
CLKA.
The CLKA1D2 output has the frequency of CLKA divided by two. CLKA1D2 is rising-edge
aligned to CLKA1.
The CLKA1D4 output has the frequency of CLKA divided by four. CLKA1D4 is rising-edge
aligned to CLKA1.
The CLKA1D8 output has the frequency of CLKA divided by eight, CLKA1D8 is rising-edge
aligned to CLKA1.
The CLKB1 output has the same frequency as the CLKB input, a delayed version of CLKB.
The skew between CLKB1 and CLKA1 is the same as the skew between CLKB and CLKA
inputs. Similarly, CLKC1 is a delayed version of CLKC, and CLKD1 is a delayed version of
CLKD.
lists the port names and description of the ports.
illustrates the PMCD primitive. The VHDL and Verilog template section
www.xilinx.com
CLKA
RST
REL
CLKB
CLKC
CLKD
Figure 3-2: PMCD Primitive
Description
PMCD Primitives, Ports, and Attributes
CLKA1D2
CLKA1D4
CLKA1D8
CLKA1
CLKB1
CLKC1
CLKD1
UG070_3_02_031208
101