XC4VFX12-10SFG363C Xilinx Inc, XC4VFX12-10SFG363C Datasheet - Page 396

• Manufacturer Part Number: XC4VFX12-10SFG363C
• Description: IC FPGA VIRTEX-4 FX 12K 363FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-10SFG363C

• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Total Ram Bits: 663552
• Number Of I /o: 240
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 363-FBGA, FCBGA
• Package: 363FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 12312
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 240
• Ram Bits: 663552
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 8: Advanced SelectIO Logic Resources
396
Timing Characteristics of 4:1 DDR 3-State Controller Serialization
Clock Event 3
The data bit A appears at OQ four CLK cycles after ABCDEFGH is sampled into the
OSERDES. This latency is consistent
OSERDES in 8:1 DDR mode is four CLK cycles.
The second word IJKLMNOP is sampled into the master and slave OSERDES from the D1–
D6 and D3–D4 inputs, respectively.
Clock Event 4
Between Clock Events 3 and 4, the entire word ABCDEFGH is transmitted serially on OQ,
a total of eight bits transmitted in one CLKDIV cycle.
The data bit I appears at OQ four CLK cycles after IJKLMNOP is sampled into the
OSERDES. This latency is consistent with
OSERDES in 8:1 DDR mode is four CLK cycles.
The operation of the 3-State Controller is illustrated in
DDR case shown in the context of a bidirectional system in which the IOB must be
frequently 3-stated.
Master.D1
Master.D2
Master.D3
Master.D4
Master.D5
Master.D6
Slave.D3
Slave.D4
CLKDIV
CLK
OQ
Figure 8-19: OSERDES Data Flow and Latency in 8:1 DDR Mode
Event 1
Clock
www.xilinx.com
G
A
B
C
D
E
F
H
Event 2
Clock
withTable
Table
8-11, which states that the latency of an
8-11, which states that the latency of an
Figure
M
N
O
K
P
J
L
I
Event 3
Clock
UG070 (v2.6) December 1, 2008
A B C D E F G H I
8-20. The example is a 4:1
Virtex-4 FPGA User Guide
UG070_c8_26_032507
Event 4
Clock
R