XC4VFX12-10SFG363C Xilinx Inc, XC4VFX12-10SFG363C Datasheet - Page 336

• Manufacturer Part Number: XC4VFX12-10SFG363C
• Description: IC FPGA VIRTEX-4 FX 12K 363FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-10SFG363C

• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Total Ram Bits: 663552
• Number Of I /o: 240
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 363-FBGA, FCBGA
• Package: 363FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 12312
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 240
• Ram Bits: 663552
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 7: SelectIO Logic Resources
336
IDELAY VHDL and Verilog Instantiation Template
safe, conservative waiting period for all modes of those modules. A closer examination of
latency for a specific path in a specific mode can trim these waiting periods down further.
If IDELAY is used in the path of a clock channel, and the delay is dynamically adjusted
during operation, every circuit that runs on that clock should be held in reset while the
delay is changed. This is because the clock may experience a short glitch when the tap
setting is incremented or decremented, and this could result in erroneous behavior in state
machines and other circuits.
If an IDELAY is used in the path of a data signal that is passing constant user traffic in
which even a single bit error is unacceptable, and the user desires to change the tap setting
in real-time, a redundant path through a second IDELAY and ISERDES (or IDDR) must be
added to the design to allow the user to switch to the redundant path while changing the
tap setting of the primary path.
VHDL and Verilog instantiation templates are available in the Libraries Guide for all
primitives and submodules.
In VHDL, each template has a component declaration section and an architecture section.
Each part of the template should be inserted within the VHDL design file. The port map of
the architecture section should include the design signals names.
VHDL for Zero-Hold Time Delay Mode
The following VHDL code shows how to instantiate the IDELAY module in a zero-hold
time delay mode.
-- Module: IDELAY
-- Description: VHDL instantiation template
-- Zero Hold Time Mode
--
-- Device: Virtex-4 Family
---------------------------------------------------------------------
-- Components Declarations
-- Component Declaration for IDELAY should be placed
-- after architecture statement but before "begin" keyword
component IDELAY
generic (IOBDELAY_TYPE : string := "DEFAULT"; --(DEFAULT, FIXED,
port (
end component;
-- Component Attribute specification for IDELAY
-- should be placed after architecture declaration but
-- before the "begin" keyword
--
);
O : out STD_LOGIC;
I : in STD_LOGIC;
C : in STD_LOGIC;
CE : in STD_LOGIC;
INC : in STD_LOGIC;
RST : in STD_LOGIC
);
VARIABLE)
IOBDELAY_VALUE : integer := 0 --(0 to 63)
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Virtex-4 FPGA User Guide
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