XC4VFX12-10SFG363C Xilinx Inc, XC4VFX12-10SFG363C Datasheet - Page 102

• Manufacturer Part Number: XC4VFX12-10SFG363C
• Description: IC FPGA VIRTEX-4 FX 12K 363FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-10SFG363C

• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Total Ram Bits: 663552
• Number Of I /o: 240
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 363-FBGA, FCBGA
• Package: 363FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 12312
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 240
• Ram Bits: 663552
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 3: Phase-Matched Clock Dividers (PMCDs)
Table 3-3: PMCD Attributes
PMCD Usage and Design Guidelines
102
RST_DEASSERT_CLK
EN_REL
PMCD Attribute Name
Phase-Matched Divided Clocks
Matched Clock Phase
Table 3-3
This section provides guidelines for using the Virtex-4 FPGA PMCD.
A PMCD produces binary-divided clocks that are rising-edge aligned to each other. From
a clock input CLKA, the PMCD derives four output clocks: a clock with the same
frequency as the original CLKA, ½, ¼, and
CLKA and the derived clocks (CLKA1, CLKA1D2, CLKA1D4, and CLKA1D8). CLKA1 is a
delayed CLKA; thus, CLKA and CLKA1 are not deskewed. CLKA1D2, CLKA1D4, and
CLKA1D8 are rising-edge aligned to CLKA1. CLKA1 reflects the duty cycle of CLKA.
However, the divided clocks (CLKA1D2, CLKA1D4, and CLKA1D8) will have a 50/50
duty cycle regardless of the CLKA duty cycle.
A PMCD allows three additional input clocks (CLKB, CLKC, CLKD) to pass through the
same delay as CLKA. Thus, the corresponding clock outputs CLKB1, CLKC1, and CLKD1
maintain the same phase relation to each other as well as the CLKA outputs (CLKA1,
CLKA1D2, CLKA1D4, CLKA1D6, and CLKA1D8) as their input. By matching the delay
inserted to all inputs, a PMCD preserves the phase relation of its divided clock to other
clocks in the design.
phase difference and the resulting PMCD outputs. CLKA1, CLKB1, CLKC1, and CLKD1
reflect the duty cycle of their corresponding input.
This attribute allows the deassertion of the RST
signal to be synchronous to a selected PMCD
input clock.
This attribute allows for CLKA1D2, CLKA1D4,
and CLKA1D8 outputs to be released at REL
signal assertion.
Note: REL is synchronous to CLKA input.
CLKA1D2
CLKA1D4
CLKA1D8
lists the PMCD attributes.
CLKA1
CLKA
Description
Figure 3-4
Figure 3-3: PMCD Frequency Divider
www.xilinx.com
T
PMCCKO_CLKIN
illustrates CLKA, CLKB, CLKC, and CLKD with a 90°
1
/
8
the frequency.
String:
CLKA, CLKB, CLKC,
or CLKD
Boolean:
FALSE, TRUE
Values
Figure 3-3
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
illustrates the input
ug070_3_03_071404
Default Value
CLKA
FALSE
R