XC4VFX12-10SFG363C Xilinx Inc, XC4VFX12-10SFG363C Datasheet - Page 399

• Manufacturer Part Number: XC4VFX12-10SFG363C
• Description: IC FPGA VIRTEX-4 FX 12K 363FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-10SFG363C

• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Total Ram Bits: 663552
• Number Of I /o: 240
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 363-FBGA, FCBGA
• Package: 363FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 12312
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 240
• Ram Bits: 663552
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
OSERDES Verilog Template
//Example OSERDES module declaration
module OSERDES (OQ, SHIFTOUT1, SHIFTOUT2, TQ, CLK, CLKDIV, D1, D2, D3,
D4, D5, D6, OCE, REV, SHIFTIN1, SHIFTIN2, SR, T1, T2, T3, T4, TCE);
);
parameter DATA_RATE_OQ = "DDR";
parameter DATA_RATE_TQ = "DDR";
parameter DATA_WIDTH = 4;
parameter INIT_OQ = 1'b0;
parameter INIT_TQ = 1'b0;
parameter SERDES_MODE = "MASTER";
parameter SRVAL_OQ = 1'b0;
parameter SRVAL_TQ = 1'b0;
parameter TRISTATE_WIDTH = 4;
output OQ;
output SHIFTOUT1;
output SHIFTOUT2;
output TQ;
input CLK;
input CLKDIV;
input D1;
input D2;
input D3;
input D4;
input D5;
input D6;
tri0 GSR = glbl.GSR;
input OCE;
input REV;
input SHIFTIN1;
input SHIFTIN2;
input SR;
input T1;
input T2;
input T3;
CLK => user_clk,
CLKDIV => user_clkdiv,
D1 => user_d1,
D2 => user_d2,
D3 => user_d3,
D4 => user_d4,
D5 => user_d5,
D6 => user_d6,
OCE => user_oce,
REV => user_rev,
SHIFTIN1 => user_shiftin1,
SHIFTIN2 => user_shiftin2,
SR => user_sr,
T1 => user_t1,
T2 => user_t2,
T3 => user_t3,
T4 => user_t4
TCE => user_tce
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Output Parallel-to-Serial Logic Resources (OSERDES)
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