XC4VFX12-10SFG363C Xilinx Inc, XC4VFX12-10SFG363C Datasheet - Page 196

• Manufacturer Part Number: XC4VFX12-10SFG363C
• Description: IC FPGA VIRTEX-4 FX 12K 363FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-10SFG363C

• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Total Ram Bits: 663552
• Number Of I /o: 240
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 363-FBGA, FCBGA
• Package: 363FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 12312
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 240
• Ram Bits: 663552
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 5: Configurable Logic Blocks (CLBs)
196
Multiplexers
Shift Register Summary
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Virtex-4 FPGA function generators and associated multiplexers can implement the
following:
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Wide input multiplexers are implemented in one level of logic (or LUT) and by dedicated
MUXFX. These multiplexers are fully combinatorial.
Each Virtex-4 FPGA slice has one MUXF5 multiplexer and one MUXFX multiplexer. The
MUXFX multiplexer implements the MUXF6, MUXF7, or MUXF8, according to the slice
position in the CLB, as shown in
multiplexers, one MUXF7 multiplexer and one MUXF8 multiplexer. MUXFX are designed
to allow LUT combinations of up to 16 LUTs in two adjacent CLBs. Any LUT can
implement a 2:1 multiplexer. Examples of multiplexers are shown in the
Multiplexers
A shift operation requires one clock edge.
Dynamic-length read operations are asynchronous (Q output).
Static-length read operations are synchronous (Q output).
The data input has a setup-to-clock timing specification.
In a cascadable configuration, the Q15 output always contains the last bit value.
The Q15 output changes synchronously after each shift operation.
4:1 multiplexer in one slice
8:1 multiplexer in two slices
16:1 multiplexer in one CLB element (4 slices)
32:1 multiplexer in two CLB elements (8 slices - 2 adjacent CLBs)
section.
www.xilinx.com
Figure
5-13. Each CLB element has two MUXF6
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
Designing Large
R