XC4VFX12-10SFG363C Xilinx Inc, XC4VFX12-10SFG363C Datasheet - Page 369

• Manufacturer Part Number: XC4VFX12-10SFG363C
• Description: IC FPGA VIRTEX-4 FX 12K 363FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-10SFG363C

• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Total Ram Bits: 663552
• Number Of I /o: 240
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 363-FBGA, FCBGA
• Package: 363FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 12312
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 240
• Ram Bits: 663552
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Clock Enable Inputs – CE1 and CE2
High-Speed Clock Input – CLK
Each ISERDES block contains an input clock enable module.
Clock Enable module.
When NUM_CE = 1, the CE2 input is not used, and the CE1 input is an active High clock
enable connected directly to the input registers in the ISERDES.
When NUM_CE = 2, the CE1 and CE2 inputs are both used, with CE1 enabling the
ISERDES for half of a CLKDIV cycle, and CE2 enabling the ISERDES for the other half.
The internal clock enable signal ICE shown in
inputs. ICE drives the clock enable inputs of registers FF0, FF1, FF2, and FF3 shown in
Figure 8-6, page
The high-speed clock input (CLK) is used to clock in the input serial data stream.
Data Bits
CLKDIV_TX
CLKDIV
CLKDIV
B
C
D
E
A
F
CE1
CE2
SR
SR
Figure 8-3: Bit Ordering at Q1–Q6 Outputs of ISERDES
373. The remaining registers in
D1
D2
D3
D4
D5
D6
OSERDES
D
AR
D
AR
Figure 8-4: Input Clock Enable Module
Q
www.xilinx.com
Q
Q
CE1R
CE2R
CLK_TX
F
Input Serial-to-Parallel Logic Resources (ISERDES)
E
D
Figure 8-4
C
Figure 8-6
B
NUM_CE
CLK_RX
1
2
2
A
is derived from the CE1 and CE2
ICE
(To ISERDES Input Registers)
do not have clock enable inputs.
Figure 8-4
CLKDIV
D
ISERDES
X
0
1
Q1
Q2
Q3
Q4
Q5
Q6
shows the Input
UG070_c8_19_041007
UG070_c8_20_032507
CE2R
CE1R
CLKDIV_RX
CE1
ICE
D
C
F
E
B
A
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